Abstract: One aspect of the invention is a terminal resistance device including a variable terminal resistance unit including a plurality of first terminal resistance elements connectable to a transmission path and a terminal resistance control unit that transmits a first control signal of a thermometer code to the variable terminal resistance unit. The first terminal resistance elements have the same resistance value and the first control signal is a signal for selecting the first terminal resistance elements to be connected to the transmission path.

Abstract: One aspect of the invention is a terminal resistance device including a variable terminal resistance unit including a plurality of first terminal resistance elements connectable to a transmission path and a terminal resistance control unit that transmits a first control signal of a thermometer code to the variable terminal resistance unit. The first terminal resistance elements have the same resistance value and the first control signal is a signal for selecting the first terminal resistance elements to be connected to the transmission path.

Abstract: The semiconductor storage device has a clock input buffer to output an internal clock signal INCLK, a NOT circuit to receive an external signal /CS, and an OR circuit to receive the output of the NOT circuit and a refresh request signal RFR and output their logical sum as an internal clock enable signal INCE to the clock input buffer. The clock input buffer has a NAND circuit to receive a clock signal CLK and the internal clock enable signal INCE and output an inverted signal of their logical product.

Abstract: The semiconductor storage device has a clock input buffer to output an internal clock signal INCLK, a NOT circuit to receive an external signal /CS, and an OR circuit to receive the output of the NOT circuit and a refresh request signal RFR and output their logical sum as an internal clock enable signal INCE to the clock input buffer. The clock input buffer has a NAND circuit to receive a clock signal CLK and the internal clock enable signal INCE and output an inverted signal of their logical product.

Abstract: A bi-directional shift register comprises flip-flops connected to first switches and second switches. Third switches are connected in sequence and between the respective flip-flops. The third switches are on-off controlled in accordance with a CLK signal in order to periodically transition from low to high or from high to low. The shift register opens the second switches during the low duration of the REV signal and opens and closes the first switches in accordance with clocking of the CLK signal to shift data in the forward direction. The shift register opens the first switches during the high duration of the REV signal and opens and closes the second switches in accordance with the clocking of the CLK signal to shift data in the reverse direction.