Abstract: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.

Abstract: A common mode noise reduction circuit works with a transmission signal output circuit that has a first and a second output terminals and transmits differential signals from the first and second output terminals. The common mode noise reduction circuit includes: a first generating circuit to generate electric current to input to or receive electric current from the first output terminal; a second generating circuit to generate electric current to input to or output receive electric current from the second output terminal; and a control circuit to control the first and second generating circuits so that in synchronism with a drive control clock of the transmission signal output circuit, the first and second generating circuits generate current pulses to reduce common mode noise of the differential signals to be transmitted.

Abstract: A common mode noise reduction circuit works with a transmission signal output circuit that has a first and a second output terminals and transmits differential signals from the first and second output terminals. The common mode noise reduction circuit includes: a first generating circuit to generate electric current to input to or receive electric current from the first output terminal; a second generating circuit to generate electric current to input to or output receive electric current from the second output terminal; and a control circuit to control the first and second generating circuits so that in synchronism with a drive control clock of the transmission signal output circuit, the first and second generating circuits generate current pulses to reduce common mode noise of the differential signals to be transmitted.

Abstract: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.

Abstract: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.

Abstract: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.

Abstract: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.

Abstract: It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal.

Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal.

Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: A skew correction apparatus is composed of a variable delay line 200 for generating a delayed clock signal DCLK by delaying a clock signal CLK by a variable delay amount DT, a phase comparator 10 for comparing a phase of the delayed clock signal DCLK with transition of rising of a data signal DAT, a voltage holding means 6 for holding a voltage Vcntl for controlling the delay amount DT of the variable delay line 200, a charging/discharging means 30 for charging or discharging the voltage holding means 6, depending on a comparison result of the phase comparator 10, a charging means 40 for setting the voltage Vcntl of the voltage holding means 6 during initial setting, and a control circuit 500 for controlling the charging means 40.

Abstract: In an amplifier circuit, a main amplification section includes an amplifier for amplifying an input signal and a reference voltage generation circuit for generating a reference voltage from an output signal of the amplifier. Other main amplification sections each including the same internal structure are cascade-connected. A switch is provided for selecting any of amplifier outputs of these main amplification sections. A frequency component lower than that of an input signal to the amplifier circuit is removed by a filter circuit, and thereafter, the presence/absence of an input signal is detected by an amplitude detection circuit and a comparator. With such a structure, even if the input signal abruptly changes, e.g., immediately after the start of communication or immediately after the end of communication, an optical signal input is correctly detected and reproduced.

Abstract: An analog equalizer includes a mixer and an analog delay circuit. The mixer mixes an input signal and a delayed signal output from the analog delay circuit to output a mixed signal. The analog delay circuit delays the mixed signal output from the mixer to output a delayed signal.

Abstract: In an amplifier circuit, a main amplification section includes an amplifier for amplifying an input signal and a reference voltage generation circuit for generating a reference voltage from an output signal of the amplifier. Other main amplification sections each including the same internal structure are cascade-connected. A switch is provided for selecting any of amplifier outputs of these main amplification sections. A frequency component lower than that of an input signal to the amplifier circuit is removed by a filter circuit, and thereafter, the presence/absence of an input signal is detected by an amplitude detection circuit and a comparator. With such a structure, even if the input signal abruptly changes, e.g., immediately after the start of communication or immediately after the end of communication, an optical signal input is correctly detected and reproduced.