Patents by Inventor Noriaki YAO
Noriaki YAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307532Abstract: Provided is a semiconductor device including a drift region of a first conductivity type which is provided in a semiconductor substrate, a buffer region of the first conductivity type which is provided in a back surface side of the semiconductor substrate relative to the drift region and which includes a first peak of a doping concentration and a second peak of the doping concentration which is provided in a front surface side of the semiconductor substrate relative to the first peak, and a first lifetime control region provided between the first peak and the second peak in a depth direction of the semiconductor substrate. An integrated concentration obtained from an upper end of the drift region to the second peak may be a critical integrated concentration or more in the depth direction of the semiconductor substrate.Type: ApplicationFiled: May 21, 2023Publication date: September 28, 2023Inventors: Noriaki YAO, Yoshihisa SUZUKI, Hiroshi TAKISHITA
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Publication number: 20230299131Abstract: A superjunction semiconductor device has: a semiconductor substrate of a first conductivity type; a buffer layer of the first conductivity type, provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate; a drift layer of the first conductivity type, provided on the buffer layer and having an impurity concentration lower than that of the buffer layer; and a parallel pn structure having first column regions of the first conductivity type and second column regions of a second conductivity type repeatedly alternating one another in a direction parallel to the front surface. A subset of the first and second column regions are located in a termination structure portion and have depths that become shallower stepwise towards an end of the semiconductor substrate, where the second column regions are provided with bottoms thereof in the drift layer.Type: ApplicationFiled: January 26, 2023Publication date: September 21, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventor: Noriaki YAO
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Publication number: 20230290816Abstract: A drift layer has a SJ structure with a parallel pn layer; an n+-type buffer layer is between the parallel pn layer and an n++-type drain layer. An impurity concentration of the n+-type buffer layer is adjusted to be at least equal to that of n-type column regions of the parallel pn layer, to be relatively low in a portion facing the parallel pn layer and approach the impurity concentration of the n-type column regions, and to increase closer to the n++-type drain layer. The impurity concentration of the n+-type buffer layer is adjusted so that an impurity concentration difference between the n+-type buffer layer and the n++-type drain layer near the border between the n+-type buffer layer and the n++-type drain layer is as small as possible. An impurity concentration distribution of the n+-type buffer layer is formed by stacking n+-type buffer layers in descending order of impurity concentration from the n++-type drain layer.Type: ApplicationFiled: January 27, 2023Publication date: September 14, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Noriaki YAO, Yuji KUMAGAI
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Publication number: 20220320324Abstract: Provided is a semiconductor device, wherein the buffer region of the semiconductor substrate has a plurality of hydrogen chemical concentration peaks arranged in different positions in the depth direction of the semiconductor substrate, a plurality of doping concentration peaks; and a high concentration region provided between the deepest hydrogen chemical concentration peak and the drift region, wherein the doping concentration distribution of the depth direction of the high concentration region has a slope where the doping concentration gradually decreases toward the drift region, wherein the slope includes a convex portion on top, wherein in an approximate concentration line that approximates a gradient of the slope with a straight line, when the concentration in a depth position of the shallowest doping concentration peak is referred to as the shallowest reference concentration, the doping concentration of the shallowest doping concentration peak is from 5% to 50% of the shallowest reference concentrationType: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Inventors: Takamasa ISHIKAWA, Noriaki YAO
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Patent number: 11063143Abstract: A method of manufacturing an insulated-gate semiconductor device includes: digging a dummy trench and digging a gate trench so as to have a U-like shape in a planar pattern to surround the dummy trench into the U-like shape; forming a dummy electrode and a gate electrode in the dummy trench and the gate trench via a gate insulating film; forming a projection for testing connected to the dummy electrode via an opening of the U-like shape and a wiring layer for testing; and testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the wiring layer for testing and a charge transport region.Type: GrantFiled: January 27, 2020Date of Patent: July 13, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takamasa Ishikawa, Noriaki Yao, Seiji Noguchi
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Publication number: 20200287029Abstract: A method of manufacturing an insulated-gate semiconductor device includes: digging a dummy trench and digging a gate trench so as to have a U-like shape in a planar pattern to surround the dummy trench into the U-like shape; forming a dummy electrode and a gate electrode in the dummy trench and the gate trench via a gate insulating film; forming a projection for testing connected to the dummy electrode via an opening of the U-like shape and a wiring layer for testing; and testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the wiring layer for testing and a charge transport region.Type: ApplicationFiled: January 27, 2020Publication date: September 10, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takamasa ISHIKAWA, Noriaki Yao, Seiji Noguchi
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Patent number: 9915961Abstract: A semiconductor device drive method achieves a balance between a lifetime and a detection sensitivity which are required for a temperature detection diode formed via an insulating film on a substrate on which an active element is formed. The semiconductor device drive method includes energizing the temperature detection diode with a constant current, the constant current having a current density value between an upper limit defined based on the lifetime of the temperature detection diode, and a lower defined based on a variation allowable voltage of an output voltage of the temperature detection diode with respect to a standard deviation.Type: GrantFiled: September 4, 2015Date of Patent: March 13, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshiyuki Matsui, Hitoshi Abe, Noriaki Yao
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Patent number: 9871110Abstract: It is aimed to reduce a current concentration at the edge of the contact electrode. Provided is a semiconductor device including a semiconductor layer, a first trench electrode formed in the semiconductor layer on a front surface side thereof, and a second trench electrode formed in the semiconductor layer on the front surface side thereof so as to oppose the first trench electrode. Here, the first trench electrode is formed in a mesh-like pattern. The semiconductor layer may further include a first-conductivity-type region and a second-conductivity-type region having a different conductivity type than the first-conductivity-type region. The first trench electrode may be electrically connected to the first-conductivity-type region, and the second trench electrode may be electrically connected to the second-conductivity-type region.Type: GrantFiled: June 15, 2016Date of Patent: January 16, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Noriaki Yao
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Patent number: 9780012Abstract: A semiconductor device includes: an interlayer insulating film covering: a cathode region and an anode region to form a pn junction with each other; a cathode electrode provided on the interlayer insulating film and connected to the cathode region through a first contact hole; and an anode electrode provided on the interlayer insulating film and connected to the anode region through a second contact hole. Among current paths in the cathode and anode regions, the current path in one of the cathode and anode regions that has a larger sheet resistance is shorter than the other current path, the current path in the cathode region extending from an interface of the pn junction to an end of the first contact hole closest to the interface, the current path in the anode region extending from the interface to an end of the second contact hole closest to the interface.Type: GrantFiled: November 10, 2014Date of Patent: October 3, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Noriaki Yao, Hitoshi Abe
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Publication number: 20170053991Abstract: It is aimed to reduce a current concentration at the edge of the contact electrode. Provided is a semiconductor device including a semiconductor layer, a first trench electrode formed in the semiconductor layer on a front surface side thereof, and a second trench electrode formed in the semiconductor layer on the front surface side thereof so as to oppose the first trench electrode. Here, the first trench electrode is formed in a mesh-like pattern. The semiconductor layer may further include a first-conductivity-type region and a second-conductivity-type region having a different conductivity type than the first-conductivity-type region. The first trench electrode may be electrically connected to the first-conductivity-type region, and the second trench electrode may be electrically connected to the second-conductivity-type region.Type: ApplicationFiled: June 15, 2016Publication date: February 23, 2017Inventor: Noriaki YAO
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Patent number: 9543289Abstract: A manufacturing method of a semiconductor device includes: depositing a thin film semiconductor layer on a semiconductor substrate with an insulating film therebetween, the insulating film having been formed on a surface of the semiconductor substrate; ion-implanting first impurity ions into the thin film semiconductor layer under a condition where a range of the first impurity ions becomes smaller than a film thickness of the thin film semiconductor layer when being deposited; and selectively ion-implanting second impurity ions into the thin film semiconductor layer with a dose quantity more than a dose quantity of the first impurity ions, in which a diode for detecting temperature is formed by a region into which the first impurity ions have been implanted and a region into which the second impurity ions have been implanted in the thin film semiconductor layer.Type: GrantFiled: May 12, 2014Date of Patent: January 10, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Noriaki Yao, Hitoshi Abe
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Publication number: 20160111348Abstract: A semiconductor device includes: an interlayer insulating film covering: a cathode region and an anode region to form a pn junction with each other; a cathode electrode provided on the interlayer insulating film and connected to the cathode region through a first contact hole; and an anode electrode provided on the interlayer insulating film and connected to the anode region through a second contact hole. Among current paths in the cathode and anode regions, the current path in one of the cathode and anode regions that has a larger sheet resistance is shorter than the other current path, the current path in the cathode region extending from an interface of the pn junction to an end of the first contact hole closest to the interface, the current path in the anode region extending from the interface to an end of the second contact hole closest to the interface.Type: ApplicationFiled: November 10, 2014Publication date: April 21, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Noriaki YAO, Hitoshi ABE
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Publication number: 20160056144Abstract: A manufacturing method of a semiconductor device includes: depositing a thin film semiconductor layer on a semiconductor substrate with an insulating film therebetween, the insulating film having been formed on a surface of the semiconductor substrate; ion-implanting first impurity ions into the thin film semiconductor layer under a condition where a range of the first impurity ions becomes smaller than a film thickness of the thin film semiconductor layer when being deposited; and selectively ion-implanting second impurity ions into the thin film semiconductor layer with a dose quantity more than a dose quantity of the first impurity ions, in which a diode for detecting temperature is formed by a region into which the first impurity ions have been implanted and a region into which the second impurity ions have been implanted in the thin film semiconductor layer.Type: ApplicationFiled: May 12, 2014Publication date: February 25, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Noriaki YAO, Hitoshi ABE
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Publication number: 20150378376Abstract: A semiconductor device drive method achieves a balance between a lifetime and a detection sensitivity which are required for a temperature detection diode formed via an insulating film on a substrate on which an active element is formed. The semiconductor device drive method includes energizing the temperature detection diode with a constant current, the constant current having a current density value between an upper limit defined based on the lifetime of the temperature detection diode, and a lower defined based on a variation allowable voltage of an output voltage of the temperature detection diode with respect to a standard deviation.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Toshiyuki MATSUI, Hitoshi ABE, Noriaki YAO