Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: According to an embodiment, a semiconductor device includes a control circuit. The control circuit is configured to receive a first command and execute, based on the first command, a first operation and a second operation. The second operation is executed after the first operation. The control circuit is further configured to output a first signal from a start of the first operation to a start of the second operation. The first signal indicates that the semiconductor device is in a busy state in which the semiconductor device refrains from accepting, from an external controller, a second command for execution of the first operation and a third command for execution of the second operation.

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: According to an embodiment, a semiconductor device includes a control circuit. The control circuit is configured to receive a first command and execute, based on the first command, a first operation and a second operation. The second operation is executed after the first operation. The control circuit is further configured to output a first signal from a start of the first operation to a start of the second operation. The first signal indicates that the semiconductor device is in a busy state in which the semiconductor device refrains from accepting, from an external controller, a second command for execution of the first operation and a third command for execution of the second operation.

Abstract: According to one embodiment, a semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first output buffer configured to output a fourth signal based on a signal selected by the first select circuit; a first output pad configured to externally output the fourth signal; and a counter configured to count a number of times the fourth signal is output.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.

Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.

Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.

Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.