Abstract: In a structure for mounting a shielded module on a printed wiring board, the shielded module includes a mounting substrate, a shielding layer, and a solder layer. Electronic components are mounted on a main surface of the mounting substrate. The shielding layer is provided in an area from above the mounting substrate to a side surface of the mounting substrate and covers the electronic components. The solder layer is provided on a side surface of the shielding layer. The shielding layer is connected to a surface electrode located on the printed wiring board via the solder layer. The surface of the solder layer is depressed.

Abstract: An electronic module includes a multilayer substrate and an FET. The multilayer substrate includes stacked substrate layers. First and second outer electrodes, a third outer electrode, and first, second, and third connecting electrodes on the multilayer substrate. The first outer electrodes and the first connecting electrode are connected to each other. The second outer electrodes and the second connecting electrode are connected to each other. The third outer electrode and the third connecting electrode are connected to each other. Terminal electrodes of the FET are connected to the first, second, and third connecting electrodes. A second capacitor electrode is between the corresponding layers of the multilayer substrate. A capacitor is defined by electrostatic capacitance between the first connecting electrode and the second capacitor electrode. An inductor is defined by via-conductors connecting the second capacitor electrode and the second connecting electrode.

Abstract: In a structure for mounting a shielded module on a printed wiring board, the shielded module includes a mounting substrate, a shielding layer, and a solder layer. Electronic components are mounted on a main surface of the mounting substrate. The shielding layer is provided in an area from above the mounting substrate to a side surface of the mounting substrate and covers the electronic components. The solder layer is provided on a side surface of the shielding layer. The shielding layer is connected to a surface electrode located on the printed wiring board via the solder layer. The surface of the solder layer is depressed.

Abstract: An electronic device that serves as a high-brightness electroluminescent device includes a layer containing a polymer compound having one or more structural units selected from a structural unit represented by formula (1) and a structural unit represented by formula (14) as a charge injection layer and/or a charge transport layer: wherein Ar1 and Ar2 represent certain fused polycyclic aromatic groups; R1, R2, R6 and R7 represent certain organic groups; m1, m2 and m6 represent an integer of 1 or more; m7 represents an integer of 0 or more; and when R1, R2, R6 and R7 are each plurally present, they each may be the same or different.

Abstract: An electronic device that serves as a high-brightness electroluminescent device includes a layer containing a polymer compound having one or more structural units selected from a structural unit represented by formula (1) and a structural unit represented by formula (14) as a charge injection layer and/or a charge transport layer: wherein Ar1 and Ar2 represent certain fused polycyclic aromatic groups; R1, R2, R6 and R7 represent certain organic groups; m1, m2 and m6 represent an integer of 1 or more; m7 represents an integer of 0 or more; and when R1, R2, R6 and R7 are each plurally present, they each may be the same or different.

Abstract: According to an embodiment, a semiconductor integrated circuit has a control section configured to execute feedback control by regulating a control parameter of a circuit section based on a temperature or an operation speed of the circuit section so that the temperature is stabilized, a history register configured to store historical data including first historical data that are time series data of the temperature, and second historical data that are time series data of the control parameter, and effectiveness determining section configured to determine effectiveness of the feedback control from the historical data.

Abstract: According to one embodiment, a design apparatus includes an extractor, a regression equation generator and an output module. The extractor extracts a critical part from a net list of a semiconductor integrated circuit. The critical part has a delay value greater than a delay threshold. The regression equation generator generates a regression equation to reproduce the delay value of the critical part using a regression algorithm. The output module outputs the regression equation.

Abstract: An organic electroluminescent device in which an organic layer containing a metal coordination compound represented by the following formula (1) is sandwiched between the pair of electrodes composed of an anode and a cathode, MLaXb??(1) wherein M is an ion of a metal of Group 11 of the Periodic Table, L is a ligand represented by the formula (2) shown below, X is an anion, and a and b are defined in the specification, wherein A is a divalent group formed by removing two hydrogen atoms from the formula (3) or (4) shown below, and D1, k1, m1, A, D1, Q1, and Q2 are defined in the specification, wherein X1, X2, X3, X4, X5, R1, R5, R6, and R9 are defined in the specification.

Abstract: A metal complex containing a nitrogen-containing aromatic ring ligand which has a dendritic molecular chain, and a copper(I) ion or a silver(I) ion. For example, the metal complex which is represented by compositional formula (8): (wherein M+ is a copper(I) ion or a silver(I) ion, L is a ligand, and X is a counter ion; p is a positive number, and q and r are each independently numerical numbers of 0 or more; R represents a hydrogen atom, a halogen atom, a cyano group, a nitro group, a carboxyl group, an amino group, an acylamino group, a silyl group, a hydroxyl group, an acyl group, a hydrocarbyl group, a hydrocarbyloxy group, a hydrocarbylthio group, or a heterocyclic group, wherein the amino group, the silyl group, the hydrocarbyl group, the hydrocarbyloxy group and the hydrocarbylthio group optionally have a substituent) has excellent heat resistance.

Abstract: An luminescent device material which is inexpensive and exhibits excellent durability in the presence of oxygen can be provided using a luminescent silver complex which has an organic multidentate ligand, particularly, a luminescent silver complex wherein the organic multidentate ligand is coordinated to a phosphorus atom, a nitrogen atom, an oxygen atom, a sulfur atom, an arsenic atom, an oxygen anion, a nitrogen anion, or a sulfur anion, or a polymer of the luminescent silver complex.

Abstract: A semiconductor test apparatus comprising: a contact-resistance calculating unit that calculates contact resistance of a measuring jig using power supply current and internal voltage obtained when power supply voltage is applied; a regression-expression calculating unit that calculates a stationary time power supply current characteristic expression using the power supply current and the internal voltage obtained when the power supply voltage is applied; and a measurement-voltage calculating unit that calculates power supply voltage for a test using operating time power supply current information, which is a corresponding relation between operating time power supply current obtained when a plurality of types of power supply voltages are applied and the types of power supply voltages, the contact resistance, and the stationary time power supply current characteristic expression.

Abstract: A semiconductor integrated circuit device comprises: a semiconductor substrate on which a semiconductor chip is provided; a plurality of phase comparators, provided on said semiconductor substrate, with input signals to said semiconductor integrated circuit from outside serving as one inputs thereof; and a variable delay circuit, provided on said semiconductor substrate, configured to adjust a timing of a reference clock signal which is used for a phase comparison; wherein distributed reference clock signal signals into which the reference clock signal is distributed so as to reach at the same time said plurality of phase comparators, are set as the other inputs of said phase comparators.

Abstract: A semiconductor integrated circuit device comprises: a semiconductor substrate on which a semiconductor chip is provided; a plurality of phase comparators, provided on said semiconductor substrate, with input signals to said semiconductor integrated circuit from outside serving as one inputs thereof; and a variable delay circuit, provided on said semiconductor substrate, configured to adjust a timing of a reference clock signal which is used for a phase comparison; wherein distributed reference clock signal signals into which the reference clock signal is distributed so as to reach at the same time said plurality of phase comparators, are set as the other inputs of said phase comparators.

Abstract: A loop circuit including a variable delay element whose delay time amount can be set arbitrarily is formed, a loop control circuit controls so that the positive/negative logic of input pulse signal to the variable delay element is always constant, the number of output of output pulse signal of the variable delay element is counted, agreement of that count value and a predetermined set value is detected, an agreement detection signal is generated when the agreement is detected, and the transmission of output pulse signal of the variable delay element to the following circuits is controlled based on this agreement detection signal.

Abstract: A logical simulation system includes delay information operating part which receives a dispersion rule file in which information on dispersion in a chip having electrical and physical characteristics which influence the operation of an integrated circuit to be analyzed is described and which receives design information of the integrated circuit to prepare a delay information file in consideration of each influence of the information on the dispersion on the basis of the dispersion rule file and the design information; and logical simulation part which receives the design information and the delay information file to carry out a logical simulation of the integrated circuit.

Abstract: A variable delay circuit comprises: a variable delay part having n (≧2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal is allowed to pass through the delay element, and an OR gate for outputting an output of the selected delay element or the input signal; and a control part for selecting at least one of the plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of the delay elements, wherein a designed delay time value Dk of the delay element of a number k (1≦k≦n) delay part meets the following conditions. Thus, it is possible to provide a smaller circuit scale of a variable delay circuit.

Abstract: A delay element testing apparatus has a signal generator for generating a plurality of signals, at least one of which is variable in timing; a phase comparator for making a comparison of a relationship in terms of phasic anteriority and posteriority between the signal passing through a delay element under test and the timing-variable signal among the plurality of signals; and a test result output circuit, controlled by a control signal generated by the phase comparator, for outputting a signal indicating a quality of a delay characteristic of the delay element under test. Main parts of this testing apparatus can be provided on a substrate to realize an integrated having a function for testing delay elements included therein.

Abstract: When defective bits of a memory are remedied, the disclosed memory analyzing apparatus can execute remedy analysis of a large capacity memory freely and effectively in a short time. Data are transferred from a defect cell memory (3) provided for a memory tester body (1) to a remedy analyzing apparatus (2) in the sequence suitable for defect remedy. The transferred data are regenerated in address sequence, and the numbers of the defective bits are counted and stored in an X line defect memory (26) and a Y line defect memory (27) at the same time. Further, a line detect flag is raised on the basis of the number of detective bits in the same row and the same column. Further, with respect to the defective bits of a line other than the defect line, the addresses thereof are stored in the bit defect memory (35), and the number of the defect bits is stored in a unit region defect number memory (33) for each defect remedy unit region.