Abstract: A semiconductor package automatic wiring apparatus which determines an optimum wiring route from each pad to a corresponding one of vias on a semiconductor package having a multi-tier bonding pad structure in which pads to be connected to a semiconductor chip are arranged in multiple rows, comprises: row identifying means for identifying each pad as to which row the pad belongs to; tentative placement means for mapping the position of the pad to a position on a matrix table after the pad has been identified by the row identifying means as to which row the pad belongs to; and determining means for determining the optimum wiring route based on the matrix table generated by the tentative placement means.

Abstract: A clearance inspection apparatus for inspecting clearance of a wiring line passing between vias on a substrate comprises: first determining means for determining vias adjacent on both sides of a reference via as first adjacent vias, the reference via and the first adjacent vias belonging to a first via row, wherein the reference via serves as a reference in clearance inspection; second determining means for determining vias adjacent to the first adjacent vias as second adjacent vias, the second adjacent vias belonging to a second via row which is adjacent to the first via row; and third determining means for determining a via located between the second adjacent vias as an inspection target via, wherein the clearance inspection apparatus inspects the clearance of the wiring line passing between the reference via and the inspection target via.

Abstract: A clearance inspection apparatus for inspecting clearance of a wiring line passing between vias on a substrate comprises: first determining means for determining vias adjacent on both sides of a reference via as first adjacent vias, the reference via and the first adjacent vias belonging to a first via row, wherein the reference via serves as a reference in clearance inspection; second determining means for determining vias adjacent to the first adjacent vias as second adjacent vias, the second adjacent vias belonging to a second via row which is adjacent to the first via row; and third determining means for determining a via located between the second adjacent vias as an inspection target via, wherein the clearance inspection apparatus inspects the clearance of the wiring line passing between the reference via and the inspection target via.

Abstract: A semiconductor package automatic wiring apparatus which determines an optimum wiring route from each pad to a corresponding one of vias on a semiconductor package having a multi-tier bonding pad structure in which pads to be connected to a semiconductor chip are arranged in multiple rows, comprises: row identifying means for identifying each pad as to which row the pad belongs to; tentative placement means for mapping the position of the pad to a position on a matrix table after the pad has been identified by the row identifying means as to which row the pad belongs to; and determining means for determining the optimum wiring route based on the matrix table generated by the tentative placement means.