Patents by Inventor Norihiko Matsushima
Norihiko Matsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11195961Abstract: The solar cell element includes a semiconductor substrate with first and second surfaces, a passivation layer being in contact with the second surface, a protective layer located on the passivation layer, a bus bar electrode, and a collecting electrode. The bus bar electrode is in contact with the second surface in a first gap portion penetrating the passivation layer and the protective layer, and is sandwiching a gap region with the passivation layer and the protective layer in a first direction along the second surface. The collecting electrode includes an electrode layer located on the protective layer, a first connecting portion located in the gap region and connecting the electrode layer and the second surface, and a second connecting portion penetrating the passivation layer and the protective layer and connecting the electrode layer and the second surface in a second gap, and is electrically connected with the bus bar electrode.Type: GrantFiled: March 26, 2019Date of Patent: December 7, 2021Assignee: KYOCERA CORPORATIONInventors: Akira Murao, Norihiko Matsushima
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Patent number: 11101392Abstract: A solar cell element is provided with a semiconductor substrate, a passivation layer, and an electrode. The semiconductor substrate has a first surface and a second surface that is positioned on a back side of the first surface. The passivation layer is positioned on the second surface of the semiconductor substrate. The electrode is positioned on the passivation layer and positioned in the state of being electrically connected to the semiconductor substrate. The electrode includes a linear electrode part that is positioned along a peripheral edge of the semiconductor substrate when the semiconductor substrate is seen from the second surface side in plane perspective view, and is positioned in the state of penetrating the passivation layer in a thickness direction.Type: GrantFiled: January 23, 2019Date of Patent: August 24, 2021Assignee: KYOCERA CORPORATIONInventors: Jumpei Sato, Akira Murao, Norihiko Matsushima
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Patent number: 10749047Abstract: The solar cell element includes a semiconductor substrate with first and second surfaces, a passivation layer located on the second surface, a protective layer located on the passivation layer, and a back-surface electrode located on the protective layer. The back-surface electrode is electrically connected to the semiconductor substrate via one or more hole portions penetrating the protective layer and the passivation layer. The protective layer includes a first region showing a tendency to increase in thickness as a distance from an inner edge portion of the hole portion and a second region surrounding the first region. A distance between a position of the first region farthest from the inner edge portion and the inner edge portion is larger than a thickness in the second region. The back-surface electrode shows a tendency to decrease in thickness on the first region as a distance from the inner edge portion.Type: GrantFiled: March 26, 2019Date of Patent: August 18, 2020Assignee: KYOCERA CORPORATIONInventors: Norihiko Matsushima, Akihiro Mizumoto, Akira Murao, Junji Aranami
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Publication number: 20190245107Abstract: The solar cell element comprises a semiconductor substrate with first and second surfaces, a passivation layer, a protective layer positioned on the passivation layer on the second surface, and a collector electrode. The collector electrode includes a first portion on the protective layer, and a second portion connected to the second surface in a plurality of hole rows each including holes that penetrate the passivation layer and the protective layer and are arranged along a first direction. When first and second hole rows adjacent in a second direction that intersects with the first direction are viewed in a plane perspective facing the second direction, the second hole row includes a third hole that overlaps a gap between first and second holes in a mutually adjacent state in the first hole row and further overlaps a part of at least one of the first and second holes.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventors: Akira MURAO, Norihiko MATSUSHIMA
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Publication number: 20190221682Abstract: The solar cell element includes a semiconductor substrate with first and second surfaces, a passivation layer located on the second surface, a protective layer located on the passivation layer, and a back-surface electrode located on the protective layer. The back-surface electrode is electrically connected to the semiconductor substrate via one or more hole portions penetrating the protective layer and the passivation layer. The protective layer includes a first region showing a tendency to increase in thickness as a distance from an inner edge portion of the hole portion and a second region surrounding the first region. A distance between a position of the first region farthest from the inner edge portion and the inner edge portion is larger than a thickness in the second region. The back-surface electrode shows a tendency to decrease in thickness on the first region as a distance from the inner edge portion.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Inventors: Norihiko Matsushima, Akihiro Mizumoto, Akira Murao, Junji Aranami
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Publication number: 20190221688Abstract: The solar cell element includes a semiconductor substrate with first and second surfaces, a passivation layer being in contact with the second surface, a protective layer located on the passivation layer, a bus bar electrode, and a collecting electrode. The bus bar electrode is in contact with the second surface in a first gap portion penetrating the passivation layer and the protective layer, and is sandwiching a gap region with the passivation layer and the protective layer in a first direction along the second surface. The collecting electrode includes an electrode layer located on the protective layer, a first connecting portion located in the gap region and connecting the electrode layer and the second surface, and a second connecting portion penetrating the passivation layer and the protective layer and connecting the electrode layer and the second surface in a second gap, and is electrically connected with the bus bar electrode.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Inventors: Akira MURAO, Norihiko MATSUSHIMA
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Publication number: 20190157475Abstract: A solar cell element is provided with a semiconductor substrate, a passivation layer, and an electrode. The semiconductor substrate has a first surface and a second surface that is positioned on a back side of the first surface. The passivation layer is positioned on the second surface of the semiconductor substrate. The electrode is positioned on the passivation layer and positioned in the state of being electrically connected to the semiconductor substrate. The electrode includes a linear electrode part that is positioned along a peripheral edge of the semiconductor substrate when the semiconductor substrate is seen from the second surface side in plane perspective view, and is positioned in the state of penetrating the passivation layer in a thickness direction.Type: ApplicationFiled: January 23, 2019Publication date: May 23, 2019Inventors: Jumpei SATO, Akira MURAO, Norihiko MATSUSHIMA
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Publication number: 20170194519Abstract: A solar cell element comprises a silicon substrate, a passivation layer, a first conductive portion, an electrode, and a second conductive portion. The silicon substrate has a plurality of recessed portions in one main surface. The passivation layer is located on the one main surface and has holes in positions corresponding to the recessed portions. The first conductive portion is located in each of the holes. The electrode is connected to the first conductive portion while being located on the passivation layer, and contains aluminum. The second conductive portion is connected to each of the silicon substrate and the first conductive portion while being located in a region in each of the recessed portions, and contains aluminum and silicon. A void in which the second conductive portion is not located is present in the region in each of the recessed portions.Type: ApplicationFiled: March 20, 2017Publication date: July 6, 2017Inventors: Norihiko MATSUSHIMA, Ryota TESHIMA, Takeshi ITO
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Patent number: 9287434Abstract: Methods for producing a semiconductor layer and for producing a photoelectric conversion device, semiconductor raw material are disclosed. An embodiment of the method for producing a semiconductor layer includes: forming a film containing a metal element and an oxygen element; generating oxygen gas by heating the film; and forming a semiconductor layer containing a metal chalcogenide from the film by allowing the metal element to react with a chalcogen element. Another embodiment of the method includes forming a lower film containing a metal element; forming an upper film, which contains the metal element and a substance that contains oxygen, on the lower film; generating oxygen gas by heating the substance; and forming a semiconductor layer containing a metal chalcogenide from the lower film and the upper film by allowing a chalcogen element to react with the metal element in the lower film and the upper film.Type: GrantFiled: June 18, 2012Date of Patent: March 15, 2016Assignee: KYOCERA CorporationInventors: Akio Yamamoto, Seiji Oguri, Hiromitsu Ogawa, Aki Kitabayashi, Shinichi Abe, Kazumasa Umesato, Norihiko Matsushima, Keizo Takeda, Manabu Kyuzo, Ken Nishiura, Atsuo Hatate
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Publication number: 20140127851Abstract: Methods for producing a semiconductor layer and for producing a photoelectric conversion device, semiconductor raw material are disclosed. An embodiment of the method for producing a semiconductor layer includes: forming a film containing a metal element and an oxygen element; generating oxygen gas by heating the film; and forming a semiconductor layer containing a metal chalcogenide from the film by allowing the metal element to react with a chalcogen element. Another embodiment of the method includes forming a lower film containing a metal element; forming an upper film, which contains the metal element and a substance that contains oxygen, on the lower film; generating oxygen gas by heating the substance; and forming a semiconductor layer containing a metal chalcogenide from the lower film and the upper film by allowing a chalcogen element to react with the metal element in the lower film and the upper film.Type: ApplicationFiled: June 18, 2012Publication date: May 8, 2014Applicant: KYOCERA CORPORATIONInventors: Akio Yamamoto, Seiji Oguri, Hiromitsu Ogawa, Aki Kitabayashi, Shinichi Abe, Kazumasa Umesato, Norihiko Matsushima, Keizo Takeda, Manabu Kyuzo, Ken Nishiura, Atsuo Hatate
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Patent number: 8674210Abstract: To provide a photoelectric conversion device having a high photoelectric conversion efficiency, a photoelectric conversion device 21 includes a substrate 1, a plurality of lower electrodes 2 on the substrate 1 comprising a metal element, a plurality of photoelectric conversion layers 33 comprising a chalcogen compound semiconductor formed on the plurality of lower electrodes 2 and separated from one another on the lower electrodes 2, a metal-chalcogen compound layer 8 comprising the metal element and a chalcogen element included in the chalcogen compound semiconductor formed between the lower electrode 2 and the photoelectric conversion layer 33, an upper electrode 5 formed on the photoelectric conversion layer 33, and a connection conductor 7 electrically connecting, in a plurality of the photoelectric conversion layers 33, the upper electrode 5 to the lower electrode 2 without interposition of the metal-chalcogen compound layer 8.Type: GrantFiled: September 29, 2010Date of Patent: March 18, 2014Assignee: Kyocera CorporationInventors: Daisuke Nishimura, Toshifumi Sugawara, Ken Nishiura, Norihiko Matsushima, Yosuke Inomata, Hisao Arimune, Tsuyoshi Uesugi
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Publication number: 20130247964Abstract: A photoelectric conversion module is disclosed. The photoelectric conversion module includes a photoelectric conversion panel and a moisture barrier plate. The photoelectric conversion panel includes first and second surfaces, a photoelectric converter between the first and second surfaces, and a conductive lead. An opening is located on the first surface. The moisture barrier plate is located on the second surface and includes first and second principal surfaces, and a through-hole extending from the first principal surface to the second principal surface. The moisture barrier plate covers the one principal surface. The through-hole does not overlap the opening. A filling member is located in a gap between the first surface and the first principal surface. The conductive lead goes through a part of the filling member, and has an end electrically coupled to the photoelectric converter and the other end coming out through the opening to the exterior.Type: ApplicationFiled: November 29, 2011Publication date: September 26, 2013Applicant: KYOCERA CORPORATIONInventors: Yosuke Inomata, Masahiro Yokota, Shintaro Mitsuno, Norihiko Matsushima, Hisao Arimune
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Publication number: 20130125982Abstract: It is aimed to provide a photoelectric conversion device having high adhesion between a light-absorbing layer and an electrode layer as well as high photoelectric conversion efficiency. A photoelectric conversion device comprises a light-absorbing layer including a chalcopyrite-based compound semiconductor and oxygen. The light-absorbing layer includes voids therein. An atomic concentration of oxygen in the vicinity of the voids is higher than an average atomic concentration of oxygen in the light-absorbing layer.Type: ApplicationFiled: July 27, 2011Publication date: May 23, 2013Applicant: KYOCERA CORPORATIONInventors: Seiji Oguri, Isamu Tanaka, Norihiko Matsushima, Akio Yamamoto
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Publication number: 20120174957Abstract: To provide a photoelectric conversion device having a high photoelectric conversion efficiency, a photoelectric conversion device 21 includes a substrate 1, a plurality of lower electrodes 2 on the substrate 1 comprising a metal element, a plurality of photoelectric conversion layers 33 comprising a chalcogen compound semiconductor formed on the plurality of lower electrodes 2 and separated from one another on the lower electrodes 2, a metal-chalcogen compound layer 8 comprising the metal element and a chalcogen element included in the chalcogen compound semiconductor formed between the lower electrode 2 and the photoelectric conversion layer 33, an upper electrode 5 formed on the photoelectric conversion layer 33, and a connection conductor 7 electrically connecting, in a plurality of the photoelectric conversion layers 33, the upper electrode 5 to the lower electrode 2 without interposition of the metal-chalcogen compound layer 8.Type: ApplicationFiled: September 29, 2010Publication date: July 12, 2012Applicant: KYOCERA CORPORATIONInventors: Daisuke Nishimura, Toshifumi Sugawara, Ken Nishiura, Norihiko Matsushima, Yosuke Inomata, Hisao Arimune, Tsuyoshi Uesugi
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Patent number: 8178778Abstract: A photovoltaic conversion element includes a one conductivity-type crystalline Si semiconductor; an opposite conductivity-type semiconductor which is joined to the crystalline Si semiconductor to form a pn junction therebetween; an electrode provided on the opposite conductivity-type semiconductor; and a depletion region formed from the side of the one conductivity-type crystalline Si semiconductor to the side of the opposite conductivity-type semiconductor across the pn junction formed therebetween. The depletion region has a first depletion region located inside the crystalline Si semiconductor and under the electrode, and the first depletion region has an oxygen concentration of 1E18 [atoms/cm3] or less.Type: GrantFiled: March 24, 2006Date of Patent: May 15, 2012Assignee: Kyocera CorporationInventors: Koichiro Niira, Tomonari Sakamoto, Norihiko Matsushima
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Publication number: 20120006389Abstract: An embodiment of a method of manufacturing a photoelectric conversion device according to the present invention includes specifying a spot having an abnormal physical property in a structure comprising a photoelectric conversion member, including a semiconductor layer, between a pair of first and second electrodes, and isolating the spot having an abnormal physical property through mechanical scribing.Type: ApplicationFiled: June 29, 2010Publication date: January 12, 2012Applicant: KYOCERA CORPORATIONInventors: Norihiko Matsushima, Daisuke Nishimura, Atsuo Hatate, Takeshi Ohkuma, Hisao Arimune, Yukari Hashimoto
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Publication number: 20090211635Abstract: A photovoltaic conversion element includes a one conductivity-type crystalline Si semiconductor; an opposite conductivity-type semiconductor which is joined to the crystalline Si semiconductor to form a pn junction therebetween; an electrode provided on the opposite conductivity-type semiconductor; and a depletion region formed from the side of the one conductivity-type crystalline Si semiconductor to the side of the opposite conductivity-type semiconductor across the pn junction formed therebetween. The depletion region has a first depletion region located inside the crystalline Si semiconductor and under the electrode, and the first depletion region has an oxygen concentration of 1E18 [atoms/cm3] or less.Type: ApplicationFiled: March 24, 2006Publication date: August 27, 2009Applicant: Kyocera CorporationInventors: Koichiro Niira, Tomonari Sakamoto, Norihiko Matsushima
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Patent number: RE46739Abstract: To provide a photoelectric conversion device having a high photoelectric conversion efficiency, a photoelectric conversion device 21 includes a substrate 1, a plurality of lower electrodes 2 on the substrate 1 comprising a metal element, a plurality of photoelectric conversion layers 33 comprising a chalcogen compound semiconductor formed on the plurality of lower electrodes 2 and separated from one another on the lower electrodes 2, a metal-chalcogen compound layer 8 comprising the metal element and a chalcogen element included in the chalcogen compound semiconductor formed between the lower electrode 2 and the photoelectric conversion layer 33, an upper electrode 5 formed on the photoelectric conversion layer 33, and a connection conductor 7 electrically connecting, in a plurality of the photoelectric conversion layers 33, the upper electrode 5 to the lower electrode 2 without interposition of the metal-chalcogen compound layer 8.Type: GrantFiled: March 17, 2016Date of Patent: February 27, 2018Assignee: KYOCERA CORPORATIONInventors: Daisuke Nishimura, Toshifumi Sugawara, Ken Nishiura, Norihiko Matsushima, Yosuke Inomata, Hisao Arimune, Tsuyoshi Uesugi