Patents by Inventor Norihiko Nagai

Norihiko Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180347385
    Abstract: A seal member assembly structure and assembly method, a seal member, and a gas turbine, wherein, in a state where first flange parts provided on a combustor transition piece are fitted into first fitting parts provided in seal members, protruding parts provided on the first flange parts are inserted into recessed parts provided in the first fitting parts.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 6, 2018
    Inventors: Hiroaki KISHIDA, Norihiko NAGAI
  • Patent number: 9430992
    Abstract: A first look-up table (10) outputs a result of dividing a horizontal component of a pixel address in the block by number of pixels in a horizontal component of the cell. A second look-up table (12) outputs a result of dividing a vertical component of a pixel address in the block by number of pixels in a vertical component of the cell. A third look-up table (14) outputs a residue as a result of dividing a horizontal component of a pixel address in the block by number of pixels in a horizontal component of the cell. A fourth look-up table (16) outputs a residue as a result of dividing a vertical component of a pixel address in the block by number of pixels in a vertical component of the cell. The output values of the first and second look-up tables (10,12) are addresses of the cell for burst access to the memory. The output values of the third and fourth look-up tables (14,16) are used as pixel addresses in the cell.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 30, 2016
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Yasuhiro Yamada, Norihiko Nagai
  • Patent number: 9286018
    Abstract: An image processing device carries out processing in a processing unit of 3-blocks. Data of 192(=64×3)-pixels is required in the processing of 3-blocks. This is an amount of data corresponding to 16-cells. When 3-blocks and 16-cells are arranged along an scanning direction of an image, both ends of them in the scanning direction are aligned.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: March 15, 2016
    Assignee: NTT Electronics Corporation
    Inventors: Yasuhiro Yamada, Norihiko Nagai
  • Publication number: 20140139536
    Abstract: A first look-up table (10) outputs a result of dividing a horizontal component of a pixel address in the block by number of pixels in a horizontal component of the cell. A second look-up table (12) outputs a result of dividing a vertical component of a pixel address in the block by number of pixels in a vertical component of the cell. A third look-up table (14) outputs a residue as a result of dividing a horizontal component of a pixel address in the block by number of pixels in a horizontal component of the cell. A fourth look-up table (16) outputs a residue as a result of dividing a vertical component of a pixel address in the block by number of pixels in a vertical component of the cell. The output values of the first and second look-up tables (10,12) are addresses of the cell for burst access to the memory. The output values of the third and fourth look-up tables (14,16) are used as pixel addresses in the cell.
    Type: Application
    Filed: March 10, 2011
    Publication date: May 22, 2014
    Applicant: NTT ELECTRONICS CORPORATION
    Inventors: Yasuhiro Yamada, Norihiko Nagai
  • Publication number: 20130088756
    Abstract: An image processing device carries out processing in a processing unit of 3-blocks. Data of 192(=64×3)-pixels is required in the processing of 3-blocks. This is an amount of data corresponding to 16-cells. When 3-blocks and 16-cells are arranged along an scanning direction of an image, both ends of them in the scanning direction are aligned.
    Type: Application
    Filed: June 7, 2011
    Publication date: April 11, 2013
    Applicant: NTT Electronics Corporation
    Inventors: Yasuhiro Yamada, Norihiko Nagai
  • Patent number: 8408002
    Abstract: A gas turbine combustor includes a pilot burner, a plurality of main burners disposed around the main burners on the radially outer side. Each of the main burners (2) includes an extension tube disposed at the downstream end. The outlet of the extension tube is shaped to have a radial edge which is parallel to the radial direction. In this manner, occurrence of flashback is effectively prevented.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: April 2, 2013
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Atsushi Moriwaki, Masataka Ohta, Keijiro Saitoh, Satoshi Tanimura, Shinji Akamatsu, Norihiko Nagai
  • Patent number: 8204105
    Abstract: A quantization step determination part inputs an evaluation value (ACT_MB) indicating the dispersion in a macroblock and its average value (ACT_PIC). A subtracter obtains the difference between these values, and a multiplier multiplies the difference by raq (<1) to obtain a weighting value. Next, an adder adds the weighting value to an average quantization step value of source data, and finally a multiplier multiplies the sum by a step value adjustment factor ? (>1) to obtain a converted quantization step value (Qstep_AVC). This optimizes a bit allocation in accordance with an Activity value of the macroblock, to thereby improve the quality of image.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: June 19, 2012
    Assignees: MegaChips Corporation, NTT Electronics Corporation
    Inventors: Hiromu Hasegawa, Nobuyuki Takasu, Mayumi Okumura, Akira Okamoto, Takashi Matsumoto, Norihiko Nagai
  • Patent number: 8072359
    Abstract: An object of the present invention is to provide a binary arithmetic coding device that allows real-time processing with a higher image quality. At a timing at which a ternary data string for a target bit is outputted, an updated coding range width and an updated range width of less probability are outputted. For that reason, while a binary conversion unit (32) and an f value retention processor (33) convert the ternary data string into a binary data string to output a coded bit, a binary arithmetic re-normalization unit (31) is allowed to perform a processing of binary arithmetic coding for the next bit.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 6, 2011
    Assignee: NTT Electronics Corporation
    Inventors: Shigeru Kasuya, Norihiko Nagai
  • Publication number: 20110122964
    Abstract: An object of the present invention is to provide a binary arithmetic coding device that allows real-time processing with a higher image quality. At a timing at which a ternary data string for a target bit is outputted, an updated coding range width and an updated range width of less probability are outputted. For that reason, while a binary conversion unit (32) and an f value retention processor (33) convert the ternary data string into a binary data string to output a coded bit, a binary arithmetic re-normalization unit (31) is allowed to perform a processing of binary arithmetic coding for the next bit.
    Type: Application
    Filed: August 20, 2008
    Publication date: May 26, 2011
    Applicant: NTT ELECTRONICS CORPORATION
    Inventors: Shigeru Kasuya, Norihiko Nagai
  • Publication number: 20080184708
    Abstract: A gas turbine combustor includes a pilot burner, a plurality of main burners disposed around the main burners on the radially outer side. Each of the main burners (2) includes an extension tube disposed at the downstream end. The outlet of the extension tube is shaped to have a radial edge which is parallel to the radial direction. In this manner, occurrence of flashback is effectively prevented.
    Type: Application
    Filed: September 1, 2005
    Publication date: August 7, 2008
    Applicant: Mitsubishi Heavy Industries, Ltd.
    Inventors: Atsushi Moriwaki, Masataka Ohta, Keijiro Saitoh, Satoshi Tanimura, Shinji Akamatsu, Norihiko Nagai
  • Publication number: 20080031337
    Abstract: A quantization step determination part inputs an evaluation value (ACT_MB) indicating the dispersion in a macroblock and its average value (ACT_PIC). A subtracter obtains the difference between these values, and a multiplier multiplies the difference by raq (<1) to obtain a weighting value. Next, an adder adds the weighting value to an average quantization step value of source data, and finally a multiplier multiplies the sum by a step value adjustment factor ? (>1) to obtain a converted quantization step value (Qstep_AVC). This optimizes a bit allocation in accordance with an Activity value of the macroblock, to thereby improve the quality of image.
    Type: Application
    Filed: July 6, 2007
    Publication date: February 7, 2008
    Applicants: MegaChips Corporation, NTT ELECTRONICS CORPORATION
    Inventors: Hiromu HASEGAWA, Nobuyuki Takasu, Mayumi Okumura, Akira Okamoto, Takashi Matsumoto, Norihiko Nagai