Abstract: A data delay circuit effectively provides a delayed serial digital data signal, with the ability to change the delay amount continuously, by delaying a lower frequency parallel data clock rather than the serial digital data signal directly. A first delay circuit 102 receives a parallel data clock which is delayed according to a first control signal to provide a delayed parallel data clock. The frequency of the parallel data clock is lower than that of a serial data clock so the first delay circuit 102 may be a delay device that provides a larger delay. A phase-locked loop 114 receives the delayed parallel data clock to generate the serial data clock in phase with the delayed parallel data clock. A parallel-to-serial converter 112 reads an n-bit parallel digital data signal from a memory 100 according to the delayed parallel data clock, and converts the parallel digital data signal to the serial digital data signal according to the serial data clock S_CLK.

Abstract: A waveform monitor receives HDTV and SDTV signals that are provided to a channel and an external trigger terminal respectively. An HDTV signal processor 14 produces a reference clock PCLK from the HDTV signal. A counter starts counting at the vertical sync signal of the SDTV signal and generates a trigger every time the count of the reference clock PCLK reaches a predetermined number (2,200, for example). This allows generation of a trigger signal which is phase locked to the vertical sync signal of the SDTV signal, and of which the frequency is the same as the horizontal line frequency of the HDTV signal. Therefore the waveform monitor can display the HDTV waveform line by line even though the HDTV and SDTV signals have different numbers of lines per field. The waveform monitor can be used to measure phase difference between television signals of difference formats, such as the HDTV and the SDTV.