Patents by Inventor Norihiko Shishido

Norihiko Shishido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080206907
    Abstract: A method for fabricating a semiconductor device includes placing a semiconductor wafer on a stage, the semiconductor wafer having a plurality of ball-shaped external connecting terminals projected from a surface, bringing a probe card close to the semiconductor wafer placed on the stage to bring a plurality of probe terminals included in the probe card into contact with the external connecting terminals respectively, and applying a voltage to the semiconductor wafer through the probe terminal to perform a test of the semiconductor wafer. The probe terminals contact all the external connecting terminals.
    Type: Application
    Filed: November 21, 2007
    Publication date: August 28, 2008
    Inventors: Norihiko Shishido, Katsu Honna, Hiroto Kotori, Shigekazu Miura
  • Publication number: 20080093722
    Abstract: An encapsulation type semiconductor device and a manufacturing method of the encapsulation type semiconductor device are disclosed. The encapsulation type semiconductor device includes a substrate provided with a concave portion which concaves in a direction from a first principal surface portion to a second principal surface portion. A first semiconductor chip using MEMS is mounted on the concave portion. A first principal surface portion of a second semiconductor chip faces at least the concave portion of the substrate with a space interposed between the first principal surface portion and the concave portion. An outer peripheral side of the concave portion of the first principal surface portion of the substrate is connected with the first principal surface portion of the second semiconductor chip facing the concave portion, by use of a connecting portion.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 24, 2008
    Inventor: Norihiko Shishido
  • Patent number: 6156622
    Abstract: In an NPN transistor of this invention having a trench isolation structure, for example, an N.sup.+ -type buried layer and an N.sup.- -type epitaxial layer are stacked on an element forming region of a P.sup.+ -type substrate, and a trench having polysilicon filled therein is formed in a portion adjacent to the element forming region. Further, a field oxide film is formed to extend from the trench having polysilicon filled therein over to the adjacent element isolation region without extending into the element forming region. Thus, a distance from the front end portion of the field oxide film on the element forming region side to the trench is reduced to reduce the element area. Therefore, the parasitic capacitance can be reduced and the power consumption of a circuit can be reduced.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: December 5, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norihiko Shishido, Sanae Yoshino
  • Patent number: 6064106
    Abstract: In an NPN transistor of this invention having a trench isolation structure, for example, an N.sup.+ -type buried layer and an N.sup.- -type epitaxial layer are stacked on an element forming region of a P.sup.+ -type substrate, and a trench having polysilicon filled therein is formed in a portion adjacent to the element forming region. Further, a field oxide film is formed to extend from the trench having polysilicon filled therein over to the adjacent element isolation region without extending into the element forming region. Thus, a distance from the front end portion of the field oxide film on the element forming region side to the trench is reduced to reduce the element area. Therefore, the parasitic capacitance can be reduced and the power consumption of a circuit can be reduced.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: May 16, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norihiko Shishido, Sanae Yoshino
  • Patent number: 5777375
    Abstract: A semiconductor device relating to an improvement in an L-PNP transistor in particular is such that, on a semiconductor substrate of a first conductivity type, a base region is formed which has a second conductivity type opposite in conductivity to the first conductivity type. A first conductivity type impurity ion is implanted into the base region to provide at least two first diffusion layers there. The first diffusion layers have a first impurity concentration level and are formed as collector and emitter regions. A polysilicon layer is formed on the first diffusion layer in base region in an overhanging relation to the first diffusion layer and contains the first conductivity type impurity. A second diffusion layer is formed around the collector region and around the emitter region by diffusing an impurity from the polysilicon layer. The collector and emitter regions each are formed as a two-layered structure with their first and second diffusion layers.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: July 7, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Norihiko Shishido
  • Patent number: D1023312
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 16, 2024
    Assignee: GC CORPORATION
    Inventors: Hiroaki Hata, Norihiko Shishido, Yurie Inaba