Abstract: A solid-state imaging device includes a plurality of pixel circuits arranged in rows and columns; and a relief unit which includes N signal lines and n pixel circuits among the plurality of pixel circuits, N being an integer greater than or equal to 3, n being an integer less than or equal to N. Each of the n pixel circuits is connected to a group of at least two signal lines out of the N signal lines, and selectively outputs a pixel signal to one of the at least two signal lines included in the group; and n groups corresponding to the n pixel circuits have mutually different combinations of signal lines, the n groups each being the group.

Abstract: A solid-state imaging device includes: a latch circuit that holds a digital signal of pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal output from the sense amplifier is to be output in normal form or in inverted form.

Abstract: A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.

Abstract: A solid-state imaging device includes a first A/D converter circuit and a second A/D converter circuit per column. The first A/D converter circuit performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal. The second A/D converter circuit performs a second A/D conversion that generates a second digital signal being a low-order portion that is a remainder of the digital signal by measuring a time required for an output of the second comparator to be inverted, the second comparator comparing a quantitative relationship between the analog signal refined and a ramp signal.

Abstract: A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.

Abstract: A solid-state imaging device includes: a latch circuit that holds a digital signal of pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal output from the sense amplifier is to be output in normal form or in inverted form.

Abstract: An imaging device includes: a pixel that outputs a pixel signal corresponding to incident light; a comparator that compares the pixel signal with a reference signal and generates an output signal that indicates a comparison result; a counter that generates a digital signal corresponding to the pixel signal by counting the number of periods until the output signal is inverted, the counter including first to fourth counter parts, each of which corresponds to one of bits included in the digital signal; a memory that stores the digital signal, the memory including first to fourth memory parts corresponding to the first to fourth counter parts; and first and second lines. The first and third counter parts are respectively connected to the first and third memory parts through the first line. The second and fourth counter parts are respectively connected to the second and fourth memory parts through the second line.

Abstract: A solid-state imaging device includes a first A/D converter circuit and a second A/D converter circuit per column. The first A/D converter circuit performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal. The second A/D converter circuit performs a second A/D conversion that generates a second digital signal being a low-order portion that is a remainder of the digital signal by measuring a time required for an output of the second comparator to be inverted, the second comparator comparing a quantitative relationship between the analog signal refined and a ramp signal.

Abstract: An imaging device includes: a pixel that outputs a pixel signal corresponding to incident light; a comparator that compares the pixel signal with a reference signal and generates an output signal that indicates a comparison result; a counter that generates a digital signal corresponding to the pixel signal by counting the number of periods until the output signal is inverted, the counter including first to fourth counter parts, each of which corresponds to one of bits included in the digital signal; a memory that stores the digital signal, the memory including first to fourth memory parts corresponding to the first to fourth counter parts; and first and second lines. The first and third counter parts are respectively connected to the first and third memory parts through the first line. The second and fourth counter parts are respectively connected to the second and fourth memory parts through the second line.

Abstract: A solid-state imaging device includes a plurality of pixels arrayed in a matrix, a plurality of first latch circuits, a first read bit line, a plurality of first driver circuits, a first amplifier, a second latch circuit, a second driver circuit, and a column scanning circuit. Each of the plurality of first latch circuits holds first pixel data which is obtained from a pixel located on the corresponding unit column. Each of the plurality of first driver circuits outputs the first pixel data, which is held in a corresponding one of the first latch circuits, to the first read bit line. The first amplifier amplifies a voltage of the first read bit line to generate first data. The second latch circuit holds the first data. The column scanning circuit sequentially outputs a plurality of the first pixel data by sequentially selecting the plurality of first driver circuits and selecting the second driver circuit.

Abstract: A solid-state imaging device includes a plurality of pixels arrayed in a matrix, a plurality of first latch circuits, a first read bit line, a plurality of first driver circuits, a first amplifier, a second latch circuit, a second driver circuit, and a column scanning circuit. Each of the plurality of first latch circuits holds first pixel data which is obtained from a pixel located on the corresponding unit column. Each of the plurality of first driver circuits outputs the first pixel data, which is held in a corresponding one of the first latch circuits, to the first read bit line. The first amplifier amplifies a voltage of the first read bit line to generate first data. The second latch circuit holds the first data. The column scanning circuit sequentially outputs a plurality of the first pixel data by sequentially selecting the plurality of first driver circuits and selecting the second driver circuit.

Abstract: A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.

Abstract: A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor.

Abstract: A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.

Abstract: A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor.

Abstract: Characteristics of both a memory cell and a peripheral circuit are degraded due to random variations, and a defective characteristic occurs in a combination of components having a substantially worst characteristic at a macro level. To solve this problem, a selector is provided between the memory cell and the peripheral circuit so that a positive phase and a negative phase of bit lines are switched at a portion where the defective characteristic occurs. Alternatively, the combination of a bit line and a sense amplifier is switched between adjacent data input/output sections, for example. In other words, the defective characteristic is repaired or corrected by canceling the combination of worst components.

Abstract: A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.

Abstract: A semiconductor memory device includes: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the memory cells; a write bit line for transmitting data to be written to one of the memory cells; an input data line for transmitting data which is received from outside and is to be written in one of the memory cells; and a selector for selectively transmitting data of the read line or the input data line to the write bit line.

Abstract: A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.

Abstract: In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.