Patents by Inventor Norihiko Yamaki

Norihiko Yamaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory employing redundant cell array of multi-bit cells
    Patent number: 8072802
    Abstract: A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: December 6, 2011
    Assignee: Spansion LLC
    Inventors: Keiichiro Kikuchi, Norihiko Yamaki, Hiroaki Wada
  • MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS
    Publication number: 20100142269
    Abstract: A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Applicant: Spansion LLC
    Inventors: Keiichiro Kikuchi, Norihiko Yamaki, Hiroaki Wada