Abstract: A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all blocks before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed.

Abstract: A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N (N is a natural number) which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation results regarding a predetermined section of at intervals of n-time; a forward-probability calculation unit that executes forward-probability calculation from time 0 to time N with respect to the coded data; and a decoded result calculation unit that calculates a decoded result of the coded data through joint-probability calculation using forward-probability calculation results by the forward-probability calculation unit and the backward-probability calculation results stored in the storage unit and backward-probability calculation results obtained through recalculation by the backward-probability calculation u

Abstract: Error detection that detects an error in an input data sequence, the input data sequence created by regarding a data sequence having a specified bit length as a polynomial, dividing that polynomial by a generator polynomial for generating error detection code and adding the error detection code to the data sequence so the remainder becomes ‘0’. Including calculating remainder values by dividing polynomials that correspond to each respective bit position by the generator polynomial and saving those remainder values; inputting together with an input data sequence, bit position information that indicates proper bit position of each data of the input data sequence, finding remainder values that correspond to proper bit positions of data of the input data sequence that are not ‘0’, performing bit-corresponding addition of each of the found remainder values; and determining no error in the input data sequence when all bits of the addition result become ‘0’.

Abstract: A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.

Abstract: A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all block before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed, and when no error is detected, the decoding results are output.

Abstract: A method of dividing an information bit string by a generator polynomial includes dividing the information bit string into a plurality of sub-bit strings A1 through AN, multiplying a remainder value by each bit of a sub-bit string Ai (1?i?N) successively with a most significant bit first so as to produce a multiplication result corresponding to the sub-bit string Ai, the remainder value being obtained by dividing a polynomial representation by the generator polynomial wherein the polynomial representation represents a bit string in which a bit position in the information bit string corresponding to a least significant bit of the sub-bit string Ai is set to “1” and remaining bit positions are set to “0”, and dividing, by the generator polynomial, a polynomial representing a bit string obtained by performing modulo-2 addition that adds up multiplication results corresponding to the sub-bit strings A1 through AN.

Abstract: A turbo decoder includes a plurality of element decoders, a memory section that stores element decoded results in matrix-patterned memory spaces, and a memory controller that writes the element decoded result of each of the element decoders in a row or column direction in the matrix-patterned memory spaces with addresses belonging to different rows being specified as writing start addresses, and reads them in the column or row direction with the addresses belonging to different rows being specified as reading start address. As a result, conflict of accesses to the memory required for an interleaving process and a deinterleaving process to be executed at the turbo decoding step can be avoided.

Abstract: A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation results regarding a predetermined section of at intervals of n-time; a forward-probability calculation unit that executes forward-probability calculation from time 0 to time N with respect to the coded data; and a decoded result calculation unit that calculates a decoded result of the coded data through joint-probability calculation using forward-probability calculation results by the forward-probability calculation unit and the backward-probability calculation results stored in the storage unit and backward-probability calculation results obtained through recalculation by the backward-probability calculation unit.

Abstract: A processor (1) having an instruction memory (2) supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (3), and address values of the registers are outputted from an address output unit (5) based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.

Abstract: The decoding device decoding coded data coded by a low density parity check code by using a plurality of parity check matrixes, comprises a pattern storing unit storing information about the parity check matrix and the segmentation pattern of the parity check matrix, which is formed by segmenting the parity check matrix into a plurality of row groups and into a plurality of column groups, and by allocating the parity check matrix so that there is one edge allocation area in the respective column groups within the respective row groups, a likelihood information storing unit storing likelihood information of respective code bits of the coded data divided into each memory cell with respect to the respective column groups, and a plurality of edge-by-edge arithmetic unit each connected to the memory cell storing the likelihood information about the column group, and updating the likelihood information based on the likelihood information stored in the connected memory cell.

Abstract: On a cathode (40) of an organic EL element, a stress reducing layer (42) formed by a material which is the same as that used for an organic layer of the organic EL element is formed. A moisture block layer (44) formed by a material which is the same as that used for the cathode (40) is then formed on the stress reducing layer (42). Thus, entering of moisture is effective prevented while the stress is reduced.

Abstract: A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.

Abstract: On a cathode (40) of an organic EL element, a stress reducing layer (42) formed by a material which is the same as that used for an organic layer of the organic EL element is formed. A moisture block layer (44) formed by a material which is the same as that used for the cathode (40) is then formed on the stress reducing layer (42). Thus, entering of moisture is effective prevented while the stress is reduced.

Abstract: A processor (1) having an instruction memory (2) supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (3), and address values of the registers are outputted from an address output unit (5) based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.

Abstract: On a cathode (40) of an organic EL element, a stress reducing layer (42) formed by a material which is the same as that used for an organic layer of the organic EL element is formed. A moisture block layer (44) formed by a material which is the same as that used for the cathode (40) is then formed on the stress reducing layer (42). Thus, entering of moisture is effective prevented while the stress is reduced.

Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.

Abstract: In a code generation device for generating a code: a binary-data generation circuit generates first binary data items indicating every (m+1)th one of n successive binary numbers, where m≧1 and n≧2. A binary-data derivation circuit derives m+1 second binary data items indicating m+1 binary numbers from each of the first binary data items, where the m+1 binary numbers include the first binary data item. A first processing circuit performs a predetermined common operation on identical portions of the m+1 second binary data items, and a second processing circuit performs individually predetermined operations on non-identical portions of the m+1 second binary data items, where states of corresponding bits in the non-identical portions of the m+1 second binary data items are not identical. A combining circuit combines the outputs of the first and second processing circuits.

Abstract: On a cathode (40) of an organic EL element, a stress reducing layer (42) formed by a material which is the same as that used for an organic layer of the organic EL element is formed. A moisture block layer (44) formed by a material which is the same as that used for the cathode (40) is then formed on the stress reducing layer (42). Thus, entering of moisture is effective prevented while the stress is reduced.

Abstract: A method of manufacturing a semiconductor device capable of preventing reduction of reliability when employing an anti-reflection coating for forming two stages of openings in an interlayer dielectric film is obtained. This method of manufacturing a semiconductor device comprises steps of forming a first resist pattern on a prescribed region of the anti-reflection coating, forming a first opening in the interlayer dielectric film through a mask of the first resist pattern, removing the first resist pattern while leaving the anti-reflection coating and thereafter forming a second resist pattern on a prescribed region of the anti-reflection coating and forming a second opening having a larger opening area than the first opening at least on an upper portion of the first opening through a mask of the second resist pattern.

Abstract: In a code generation device for generating a code: a binary-data generation circuit generates first binary data items indicating every (m+1)th one of n successive binary numbers, where m≧1 and n≧2. A binary-data derivation circuit derives m+1 second binary data items indicating m+1 binary numbers from each of the first binary data items, where the m+1 binary numbers include the first binary data item. A first processing circuit performs a predetermined common operation on identical portions of the m+1 second binary data items, and a second processing circuit performs individually predetermined operations on non-identical portions of the m+1 second binary data items, where states of corresponding bits in the non-identical portions of the m+1 second binary data items are not identical. A combining circuit combines the outputs of the first and second processing circuits.