Abstract: A semiconductor module, including: a first circuit board and a second circuit board respectively have a first switching element and a second switching element located thereon, each of the first and second switching elements having an emitter electrode; a first connecting portion and a second connecting portion respectively electrically connected to the emitter electrodes of the first and second switching elements over the first and second circuit boards; an auxiliary emitter terminal; and an auxiliary emitter wiring electrically connected to the auxiliary emitter terminal. The auxiliary emitter wiring includes: a branch point, a common wiring portion which connects the auxiliary emitter terminal and the branch point, and a first discrete wiring portion and a second discrete wiring portion which connect the branch point respectively to the first and second connecting portions, and which each have an inductance smaller than 10 percent of an inductance of the common wiring portion.

Abstract: Provided is a semiconductor device including: a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; a first main terminal provided above the upper surface; a second main terminal provided below the lower surface; a control terminal configured to control whether or not to cause a current to flow between the first main terminal and the second main terminal; and a buffer region provided between the drift region and the lower surface and having a higher doping concentration than the drift region. In a C-V characteristic indicating a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal, a region where the power supply voltage is 500 V or more has a peak of the inter-terminal capacitance.

Abstract: Provided is a manufacturing method of a semiconductor device, the manufacturing method including implanting a first dopant of a first conductivity type from an implantation surface of a semiconductor substrate into a first implantation position and implanting a second dopant of the first conductivity type from the implantation surface of the semiconductor substrate into a second implantation position having a larger distance from the implantation surface than the first implantation position after implanting the first dopant. The first implantation position and the second implantation position may be arranged in the buffer region.

Abstract: Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

Abstract: Provided is a semiconductor device including: a semiconductor substrate having a drift region of a first conductivity type; and a buffer region of the first conductivity type provided between the drift region and a lower surface of the semiconductor substrate and having a higher doping concentration than the drift region. The buffer region has two or more helium chemical concentration peaks arranged at different positions in a depth direction of the semiconductor substrate.

Abstract: A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.

Abstract: Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

Abstract: There is provided a semiconductor device including: a drift region of a first conductivity type disposed in a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed above the base region; a plurality of trench portions arrayed in a predetermined array direction on a front surface side of the semiconductor substrate; a trench contact disposed on the front surface side of the semiconductor substrate between two adjacent trench portions; and a contact layer of the second conductivity type disposed under the trench contact and having a higher doping concentration than the base region, wherein a lower end of the trench contact is deeper than a lower end of the emitter region, and the emitter region and the contact layer are in contact with each other at a side wall of the trench contact.

Abstract: Provided is a semiconductor device that has a plurality of gate trench portions electrically connected to a gate electrode, and a plurality of dummy trench portions electrically connected to an emitter electrode, and includes a first trench group that includes one gate trench portion and two dummy trench portions adjacent to the gate trench portion and adjacent to each other, and a second trench group that includes two gate trench portions adjacent to each other.