Patents by Inventor Norihiro NASHIDA

Norihiro NASHIDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230008663
    Abstract: A semiconductor module includes first and second semiconductor chips including first and second main electrodes, respectively; first and second connection terminals electrically connected to the first and second main electrodes, respectively; and an insulating sheet. The first connection terminal includes a first conductor portion including a first peripheral edge and a first terminal portion extending from the first peripheral edge in plan view, and the second connection terminal includes a second conductor portion including a second peripheral edge. A part of the first conductor portion overlap a part of the second conductor portion in plan view. The insulating sheet includes an insulating portion layered between the first and second conductor portions, and a first protruding portion positioned between a tip portion of the first terminal portion and the second peripheral edge in plan view, the first protruding portion forming an angle relative to a surface of the first terminal portion.
    Type: Application
    Filed: May 24, 2022
    Publication date: January 12, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Tadahiko SATO, Norihiro NASHIDA
  • Patent number: 10903130
    Abstract: A semiconductor apparatus 1 includes a circuit substrate 3 having a circuit pattern layer 3c on an upper principal surface, semiconductor elements 4a and 4b mounted on the circuit pattern layer 3c of the circuit substrate 3, a printed substrate 6 arranged apart from the circuit substrate 3 on the upper principal surface side of the circuit substrate 3, a housing 2 mold-sealing the upper principal surface side of the circuit substrate 3, and a block 10 provided sandwiching at least part of the housing 2 and being opposite to the circuit substrate 3, the block having a linear expansion coefficient smaller than that of the housing 2.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: January 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoko Nakamura, Norihiro Nashida, Yuichiro Hinata
  • Publication number: 20190300999
    Abstract: A method of forming a metallic film is provided. The method includes: controlling gas conditions in a processing vessel in which a substrate is disposed on a stage; performing a pretreatment by spraying a plasma jet on the substrate in the processing vessel, the plasma jet being generated from gas containing an inert gas and hydrogen; and thermal spraying metallic material on the substrate while heating the stage at 100° C. or higher, the thermal spraying being performed after the pretreatment.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Eiji YAMAGUCHI, Tsunehiro NAKAJIMA, Yoichi RYOKAI, Norihiro NASHIDA
  • Patent number: 10079155
    Abstract: A semiconductor device manufacturing method, sequentially includes a semiconductor element preparation step of preparing a first semiconductor element on which is formed a plurality of metal electrodes, a step of covering a surface of the first semiconductor element on which the metal electrode is not formed with a first insulating member, and a step of forming a second metal layer that conductively connects the metal electrode of the first semiconductor element and a first metal layer on an insulated circuit substrate across the second insulating member.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 18, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsunehiro Nakajima, Yoshikazu Takahashi, Norihiro Nashida
  • Patent number: 10068870
    Abstract: A semiconductor device includes a plurality of semiconductor units each including a laminated substrate formed by laminating an insulating board and a circuit board and a semiconductor element joined to the circuit board using a joining material which irreversibly makes a phase transition into a solid-phase state. In addition, the semiconductor device may include a base plate to which each of the plurality of semiconductor units is joined using solder and a connection unit which electrically connects the plurality of semiconductor units in parallel.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Norihiro Nashida, Hideyo Nakamura, Yoko Nakamura
  • Patent number: 9991220
    Abstract: The semiconductor device includes an insulating substrate including an insulating plate and a circuit plate; a semiconductor chip having a front surface formed with an electrode and a rear surface fixed to the circuit plate; a printed circuit board including a metal layer, and facing the insulating substrate; a conductive bonding material disposed on the electrode; and a conductive post having a leading end portion electrically and mechanically connected to the electrode through the bonding material, a base portion electrically and mechanically connected to the metal layer, and a central portion. In the conductive post, a wetting angle of a surface of the leading end portion with respect to the molten bonding material is less than the wetting angle of a surface of the central portion.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 5, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoko Nakamura, Norihiro Nashida
  • Publication number: 20180114735
    Abstract: A semiconductor apparatus 1 includes a circuit substrate 3 having a circuit pattern layer 3c on an upper principal surface, semiconductor elements 4a and 4b mounted on the circuit pattern layer 3c of the circuit substrate 3, a printed substrate 6 arranged apart from the circuit substrate 3 on the upper principal surface side of the circuit substrate 3, a housing 2 mold-sealing the upper principal surface side of the circuit substrate 3, and a block 10 provided sandwiching at least part of the housing 2 and being opposite to the circuit substrate 3, the block having a linear expansion coefficient smaller than that of the housing 2.
    Type: Application
    Filed: August 30, 2017
    Publication date: April 26, 2018
    Inventors: Yoko NAKAMURA, Norihiro NASHIDA, Yuichiro HINATA
  • Patent number: 9852968
    Abstract: The semiconductor device includes an insulating substrate on which is mounted a main circuit part including a semiconductor chip, a printed substrate wherein a conductive connection member connected to the semiconductor chip is disposed on the surface opposing the insulating substrate, a first sealing member that seals so as to enclose the semiconductor chip between the opposing surfaces of the insulating substrate and printed substrate, and a second sealing member that covers the whole excepting a bottom portion of the insulating substrate, the semiconductor device having sealing region regulation rod portions disposed in an outer peripheral portion of a sealing region of the first sealing member and connected between the insulating substrate and printed substrate, wherein the heat resistance temperature of the first sealing member is set to be higher than the heat resistance temperature of the second sealing member.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Norihiro Nashida
  • Publication number: 20170365547
    Abstract: A semiconductor device comprises a semiconductor element 12 including electrodes 12G, 12S on a front surface and conductive posts 14, 14?, 14? including one end which is soldered to electrodes 12G, 12S of the semiconductor element 12. The conductive posts 14, 14?, 14? includes a solder absorbing portion 14b having a larger surface area per unit length than that of a bottom portion at a position apart from the one end by a length equal to a height of a bottom portion 14a in an extending direction. When the conductive post is joined by a solder, the solder melted and flowing across a surface of the conductive post is absorbed in a large surface of the solder absorbing portion, thereby preventing the solder from reaching a wiring substrate.
    Type: Application
    Filed: April 28, 2017
    Publication date: December 21, 2017
    Inventors: Yoko NAKAMURA, Norihiro NASHIDA
  • Publication number: 20170309496
    Abstract: A semiconductor device manufacturing method, sequentially includes a semiconductor element preparation step of preparing a first semiconductor element on which is formed a plurality of metal electrodes, a step of covering a surface of the first semiconductor element on which the metal electrode is not formed with a first insulating member, and a step of forming a second metal layer that conductively connects the metal electrode of the first semiconductor element and a first metal layer on an insulated circuit substrate across the second insulating member.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 26, 2017
    Inventors: Tsunehiro NAKAJIMA, Yoshikazu TAKAHASHI, Norihiro NASHIDA
  • Patent number: 9773767
    Abstract: A semiconductor device includes an insulating substrate including an insulating plate and a circuit plate disposed on a main surface of the insulating plate; a semiconductor chip having a front surface provided with an electrode and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate and including a metal layer; a conductive post having one end electrically and mechanically connected to the electrode and another end electrically and mechanically connected to the metal layer; a passive element fixed to the printed circuit board; and a plurality of positioning posts fixed to the printed circuit board to position the passive element.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoko Nakamura, Norihiro Nashida
  • Patent number: 9741587
    Abstract: Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the semiconductor device can be reduced. The semiconductor device includes an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer, a metal plate conductively connected to the first metal layer, a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes, a first insulating member disposed on a side surface of the first semiconductor element, a second insulating member disposed on the first insulating member and on the first semiconductor element, and a third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 22, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsunehiro Nakajima, Yoshikazu Takahashi, Norihiro Nashida
  • Patent number: 9648732
    Abstract: A semiconductor device includes: a conductive-patterned insulating substrate; conductive blocks fixed to conductive patterns of the conductive-patterned insulating substrate; a semiconductor chip fixed to each conductive block; a printed circuit board that has a conductive post fixed to the semiconductor chip; and a resin. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 9, 2017
    Assignee: FUJI ELECTRIC CO, LTD.
    Inventors: Youko Nakamura, Norihiro Nashida
  • Patent number: 9640454
    Abstract: A semiconductor device includes an insulating substrate having a circuit plate on a principal surface thereof; a semiconductor element fixed to the circuit plate; an external terminal having one end fixed to the circuit plate; and a printed circuit board facing the principal surface of the insulating substrate, and having a through-hole for passing through the external terminal. A rigidity of a peripheral region of the through-hole is lower than a rigidity of other regions.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 2, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Norihiro Nashida, Yoko Nakamura
  • Patent number: 9627342
    Abstract: Plating pre-processing is carried out before carrying out a plating process on the surface of a conducting section provided on a semiconductor wafer. A first metal film is formed on the surface of the conducting section by NiP alloy plating process. A second metal film is formed on the surface of the first metal film by immersion Ag plating process. The semiconductor wafer is diced and cut into semiconductor chips. A conductive composition containing Ag particles is applied to the surface of the second metal film which is on the front surface of the semiconductor chip. A bonding layer containing Ag particles is formed by sintering the conductive composition through heating. A metal plate is then bonded to the surface of the second metal film via the bonding layer containing Ag particles. The electronic component has high bonding strength, excellent thermal resistance and heat radiation properties.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 18, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Tatsuo Nishizawa, Yoshito Kinoshita, Norihiro Nashida
  • Publication number: 20170053871
    Abstract: Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the semiconductor device can be reduced. The semiconductor device includes an insulated circuit substrate having on one main surface thereof a first metal layer and a second metal layer, a metal plate conductively connected to the first metal layer, a first semiconductor element including on front and rear surfaces thereof a plurality of metal electrodes, a first insulating member disposed on a side surface of the first semiconductor element, a second insulating member disposed on the first insulating member and on the first semiconductor element, and a third metal layer, in which at least one portion thereof is disposed on the second insulating member and which conductively connects the metal electrode of the first semiconductor element and the second metal layer on the insulated circuit substrate.
    Type: Application
    Filed: July 8, 2016
    Publication date: February 23, 2017
    Inventors: Tsunehiro NAKAJIMA, Yoshikazu TAKAHASHI, Norihiro NASHIDA
  • Publication number: 20170018524
    Abstract: A semiconductor device includes a plurality of semiconductor units each including a laminated substrate formed by laminating an insulating board and a circuit board and a semiconductor element joined to the circuit board using a joining material which irreversibly makes a phase transition into a solid-phase state. In addition, the semiconductor device may include a base plate to which each of the plurality of semiconductor units is joined using solder and a connection unit which electrically connects the plurality of semiconductor units in parallel.
    Type: Application
    Filed: March 4, 2016
    Publication date: January 19, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Norihiro NASHIDA, Hideyo NAKAMURA, Yoko NAKAMURA
  • Patent number: 9418916
    Abstract: A semiconductor device including a semiconductor chip, a first electrode pad and second electrode pad included on one surface of the semiconductor chip, a first conductive post joined by a joining material to the first electrode pad, a plurality of second conductive posts joined by a joining material to the second electrode pad, and a printed substrate, disposed opposing the one surface of the semiconductor chip, on which is formed an electrical circuit to which the first conductive post and second conductive posts are connected. The second conductive posts on the side near the first conductive post are arrayed avoiding a short-circuit prevention region at a distance such that the joining material of the first conductive post and the joining material of the second conductive posts do not link.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: August 16, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoko Nakamura, Norihiro Nashida
  • Patent number: 9355987
    Abstract: A first metal film, of which major component is copper, is formed on a surface of a conductive portion which becomes a front surface electrode of a semiconductor element. A second metal film of which major component is silver is formed on a surface of the first metal film. A metal plate, which electrically connects the conductive portion and the other members (e.g. a circuit pattern of an insulated substrate) is bonded with a surface of the second metal film via a bonding layer containing silver particles. The second metal film does not contain nickel which decreases the bonding strength between the second metal film and the bonding layer containing silver particles. With the above configuration, an electronic component having a high bonding strength, excellent heat resistance and radiation performance, and a manufacturing method for the electronic component can be provided.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 31, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Tatsuo Nishizawa, Yoshito Kinoshita, Norihiro Nashida
  • Publication number: 20160079133
    Abstract: A semiconductor device includes an insulating substrate having a circuit plate on a principal surface thereof; a semiconductor element fixed to the circuit plate; an external terminal having one end fixed to the circuit plate; and a printed circuit board facing the principal surface of the insulating substrate, and having a through-hole for passing through the external terminal. A rigidity of a peripheral region of the through-hole is lower than a rigidity of other regions.
    Type: Application
    Filed: November 5, 2015
    Publication date: March 17, 2016
    Inventors: Norihiro NASHIDA, Yoko NAKAMURA