Patents by Inventor Norihiro Uemura

Norihiro Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140366709
    Abstract: In an ensemble performance, performance lesson or the like, a musical score (display content) is displayed and input audio is recorded. The input audio includes notes, comments or the like uttered by a human player or an instructor. During recording of the input audio is received a user input designating a desired time position on the musical score displayed on the display device. A recording time of the input audio based on a time point at which the user input has been received and the time position on the musical score designated by the user input are stored into a storage device in association with each other. An icon is displayed in association with the time position on the musical score designated by the user input. Once the icon is selected, voice based on the recording time recorded in association with the icon is reproduced to sound the comments, etc.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 18, 2014
    Inventor: Norihiro UEMURA
  • Publication number: 20140362059
    Abstract: A thin film transistor includes a drain electrode layer and a source electrode layer that are formed above an oxide semiconductor layer via an insulating film. The drain electrode layer and the source electrode layer are electrically connected with the oxide semiconductor layer via through-holes formed in the insulating film. A first through-hole that electrically connects the drain electrode layer with the oxide semiconductor layer and a second through-hole that electrically connects the source electrode layer with the oxide semiconductor layer each include two or more through-holes that are arranged in parallel in a channel width direction of the thin film transistor. A total width of opening widths of the first or second through-holes in the channel width direction is a channel width of the thin film transistor.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 11, 2014
    Inventors: Norihiro UEMURA, Hidekazu MIYAKE, Takeshi NODA, Isao SUZUMURA, Yohei YAMAGUCHI
  • Publication number: 20140307194
    Abstract: In a bottom gate thin film transistor using a first oxide semiconductor layer as a channel layer, the first oxide semiconductor layer and second semiconductor layers include In and O. An (O/In) ratio of the second oxide semiconductor layers is equal to or larger than that of the first oxide semiconductor layer, and a film thickness thereof is thicker than that of the first oxide semiconductor layer.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 16, 2014
    Applicant: Japan Display Inc.
    Inventors: Isao SUZUMURA, Norihiro UEMURA, Takeshi NODA, Hidekazu MIYAKE, Yohei YAMAGUCHI
  • Patent number: 8853012
    Abstract: A gate insulating film has a convex portion conforming to a surface shape of a gate electrode and a step portion that changes in height from a periphery of the gate electrode along the surface of the gate electrode. An oxide semiconductor layer is disposed on the gate insulating film so as to have a transistor constituting region having a channel region, a source region, and a drain region in a continuous and integral manner and a covering region being separated from the transistor constituting region and covering the step portion of the gate insulating film. A channel protective layer is disposed on the channel region of the oxide semiconductor layer. A source electrode and a drain electrode are disposed in contact respectively with the source region and the drain region of the oxide semiconductor layer. A passivation layer is disposed on the source electrode and the drain electrode.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: October 7, 2014
    Assignee: Japan Display Inc.
    Inventors: Norihiro Uemura, Takeshi Noda, Hidekazu Miyake, Isao Suzumura
  • Publication number: 20140054583
    Abstract: A gate insulating film has a convex portion conforming to a surface shape of a gate electrode and a step portion that changes in height from a periphery of the gate electrode along the surface of the gate electrode. An oxide semiconductor layer is disposed on the gate insulating film so as to have a transistor constituting region having a channel region, a source region, and a drain region in a continuous and integral manner and a covering region being separated from the transistor constituting region and covering the step portion of the gate insulating film. A channel protective layer is disposed on the channel region of the oxide semiconductor layer. A source electrode and a drain electrode are disposed in contact respectively with the source region and the drain region of the oxide semiconductor layer. A passivation layer is disposed on the source electrode and the drain electrode.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 27, 2014
    Applicant: Japan Display Inc.
    Inventors: Norihiro UEMURA, Takeshi NODA, Hidekazu MIYAKE, Isao SUZUMURA
  • Publication number: 20130340593
    Abstract: A plurality of sets of waveform data and switchover position information indicative of, for each of the sets of waveform data, one or more possible switchover positions in the waveform data are prestored, and one set of waveform data is reproduced in accordance with the passage of time. During reproduction of a first set of waveform data, a second set of waveform data is designated at given timing in response to a user's instruction. Control is performed such that the waveform data to be reproduced is switched from the first set of waveform data over to the second set of waveform data in response to waveform data reproduction timing arriving at one of the possible switchover positions indicated by the switchover position information corresponding to the second set of waveform data. Reproduction of the second set of waveform data is started at the switchover position corresponding to the reproduction timing.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 26, 2013
    Inventors: Norihiro UEMURA, Takashi MIZUHIKI, Kazuhiko YAMAMOTO, Atsuhiko MATSUSHITA
  • Publication number: 20130340594
    Abstract: Waveform data are stored in advance together with reference position information indicative of reference positions, in the waveform data, corresponding to reference timing, such as beat timing, and correction position information indicative of correction positions in the waveform data that are different from the reference positions. The reference timing is advanced when the waveform data are reproduced. In response to arrival of the reference timing, a deviation between a reproduction position of the currently reproduced waveform data and the reference position is evaluated. When the reproduction position arrives at the correction position, the reproduction position is corrected according to the evaluated deviation.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 26, 2013
    Inventors: Norihiro UEMURA, Takashi MIZUHIKI, Kazuhiko YAMAMOTO, Atsuhiko MATSUSHITA
  • Publication number: 20130334524
    Abstract: The present invention provides a display device having: gate electrodes formed on a transparent substrate; a gate insulating film for covering the gate electrodes; an oxide semiconductor formed on the gate insulating film; drain electrodes and source electrodes formed at a distance from each other with channel regions of the oxide semiconductor in between; an interlayer capacitor film for covering the drain electrodes and source electrodes; common electrodes formed on top of the interlayer capacitor film; and pixel electrodes formed so as to face the common electrodes, and wherein an etching stopper layer for covering the channel regions is formed between the oxide semiconductor and the drain electrodes and source electrodes, the drain electrodes are a multilayer film where a transparent conductive film and a metal film are layered on top of each other, and the drain electrodes and source electrodes make direct contact with the oxide semiconductor.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 19, 2013
    Inventors: Hidekazu MIYAKE, Norihiro UEMURA, Takeshi NODA, Isao SUZUMURA, Toshiki KANEKO
  • Publication number: 20130278855
    Abstract: A thin film transistor includes, an insulating substrate, a gate electrode provided on an upper surface of the insulating substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer provided on the gate insulating film, a channel protective layer provided at least on an upper surface of the oxide semiconductor layer, and a source electrode and a drain electrode provided so as to come into contact with the oxide semiconductor layer, wherein the channel protective layer is formed such that the film density of a portion provided so as to come into contact with the oxide semiconductor layer is higher than the film density of a portion distant from the oxide semiconductor layer.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 24, 2013
    Applicant: Japan Display East Inc.
    Inventors: Norihiro UEMURA, Takeshi NODA, Hidekazu MIYAKE, Isao SUZUMURA
  • Publication number: 20120223315
    Abstract: Disclosed is a display device including: a gate electrode; a semiconductor layer formed into an island shape on an upper side of the gate electrode; a side wall oxide film formed on a lateral surface of the semiconductor layer; and a drain electrode and a source electrode formed on an upper side of the semiconductor layer extending from a lateral side of the semiconductor layer, wherein the side wall oxide film has a thickness of 2.1 nm or more.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Inventors: Norihiro UEMURA, Hidekazu MIYAKE, Isao SUZUMURA, Takeshi KURIYAGAWA
  • Patent number: 8259257
    Abstract: The liquid crystal display apparatus includes a liquid crystal panel and the back light device for emitting the light from a light source to the liquid crystal panel through a lens. The light source includes a first LED for emitting the light of a first color, a second LED for emitting the light of a second color, a third LED for emitting the light of a third color, a fourth LED for emitting the light of the third color, a fifth LED for emitting the light of the second color, and a sixth LED for emitting the light of the first color. The first, second, third, fourth, fifth and sixth LEDs are arranged on the wiring board in such a manner as to offset the deviation of the light distribution.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Yutaka Akiba, Ikuo Hiyama, Kiyomi Nakamura, Yoshinori Aono, Makoto Tsumura, Akitoyo Konno, Norihiro Uemura
  • Patent number: 8098013
    Abstract: A plasma display device includes: a front substrate and a back substrate facing each other and interposing a discharge gap; and a plurality of discharge cells formed by the front substrate and the back substrate, wherein a mixture gas containing Xe is filled in the discharge gap, and a red, green, or blue phosphor materials is arranged in each of the discharge cells. The plasma display device performs a reset operation by, at least, a weak discharge. A crystal material is arranged in the red, green, and blue phosphor materials so as to make weak discharge firing voltages for reset discharges in respective discharge cells uniform.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: January 17, 2012
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Norihiro Uemura, Shunichiro Nobuki, Naoya Tokoo, Masakazu Sagawa
  • Patent number: 8085220
    Abstract: A plasma display apparatus having a priming discharge region PDC partitioned from a display discharge cell DDC, by a traverse rib, at a side where the second electrode between the display discharge cell DDC adjacent in a row direction is adjacent; a second longitudinal rib partitioning the priming discharge region PDC; a third longitudinal rib, further partitioning a region partitioned by the second longitudinal rib into two sections; a convex electrode; and a gap connecting the display discharge cell DDC and the priming discharge cell PDC, wherein a sum of a width in a line direction of a nearly rectangular space region containing adjacent two priming discharge cells PDCs, and a pattern width of the second longitudinal rib is designed larger than a sum of a width in the row direction and a pattern width of the traverse rib.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: December 27, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Shunichiro Nobuki, Norihiro Uemura, Masakazu Sagawa, Keizo Suzuki, Yoshiro Mikami, Hideto Momose, Shirun Ho
  • Publication number: 20100066943
    Abstract: The liquid crystal display apparatus includes a liquid crystal panel and the back light device for emitting the light from a light source to the liquid crystal panel through a lens. The light source includes a first LED for emitting the light of a first color, a second LED for emitting the light of a second color, a third LED for emitting the light of a third color, a fourth LED for emitting the light of the third color, a fifth LED for emitting the light of the second color, and a sixth LED for emitting the light of the first color. The first, second, third, fourth, fifth and sixth LEDs are arranged on the wiring board in such a manner as to offset the deviation of the light distribution.
    Type: Application
    Filed: August 17, 2009
    Publication date: March 18, 2010
    Inventors: Yutaka AKIBA, Ikuo Hiyama, Kiyomi Nakamura, Yoshinori Aono, Makoto Tsumura, Akitoyo Konno, Norihiro Uemura
  • Publication number: 20100013370
    Abstract: Provided is a plasma display device which is bright and has high contrast and high image quality. A plasma display device includes: a front substrate and a back substrate facing each other interposing a discharge gap; and a plurality of discharge cells formed by the front substrate and the back substrate, wherein a mixture gas containing Xe is filled in the discharge gap, and each of a plurality of phosphor layers of red, green, and blue is arranged in the discharge cell. And, the plasma display device performs a reset operation by, at least, a weak discharge. A crystal material is arranged in the phosphor layers of red, green, and blue so as to uniform weak discharge firing voltages for reset discharges in respective discharge cells.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 21, 2010
    Applicant: HITACHI CONSUMER ELECTRONICS CO., LTD.
    Inventors: Norihiro UEMURA, Shunichiro NOBUKI, Naoya TOKOO, Masakazu SAGAWA
  • Publication number: 20090225008
    Abstract: A plasma display apparatus having a priming discharge region PDC partitioned from a display discharge cell DDC, by a traverse rib, at a side where the second electrode between the display discharge cell DDC adjacent in a row direction is adjacent; a second longitudinal rib partitioning the priming discharge region PDC; a third longitudinal rib, further partitioning a region partitioned by the second longitudinal rib into two sections; a convex electrode; and a gap connecting the display discharge cell DDC and the priming discharge cell PDC, wherein a sum of a width in a line direction of a nearly rectangular space region containing adjacent two priming discharge cells PDCs, and a pattern width of the second longitudinal rib is designed larger than a sum of a width in the row direction and a pattern width of the traverse rib.
    Type: Application
    Filed: November 26, 2008
    Publication date: September 10, 2009
    Inventors: Shunichiro Nobuki, Norihiro Uemura, Masakazu Sagawa, Keizo Suzuki, Yoshiro Mikami, Hideto Momose, Shirun Ho
  • Publication number: 20090184895
    Abstract: A high-definition, high-quality, and high-contrast PDP that features high brightness, guaranteed long life, and stable driving, is provided by improving the time-dependent degradation of address discharge delay. The PDP includes: a front substrate having bus electrodes, and sustain discharge electrodes extending in a lateral direction of the bus electrodes to form display lines; a back substrate having address electrodes facing the sustain discharge electrodes in the lateral direction of the bus electrodes; and discharge cells formed between the substrates. Each of the discharge cells includes a sustain discharge cell and a priming discharge cell, in which a protruding electrode is formed to extend in a direction opposite to the discharge gap from the bus electrode, and a predetermined space is provided between the two cells to supply priming. The shape and size of the space are optimized so that the sustain discharge does not spread to the address discharge cell through the space.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 23, 2009
    Inventors: Norihiro Uemura, Shunichiro Nobuki, Masakazu Sagawa, Shirun Ho, Keizo Suzuki, Yoshiro Mikami
  • Publication number: 20090079672
    Abstract: There is provided a PDP, in which the deterioration in the address discharge timelag with age is suppressed, which is bright, has guaranteed life, can stably be driven, is of low power consumption, high definition, and high image quality. There is provided a pair of sustaining discharge electrodes on the front substrate extending in a row direction for forming a display line, a floating electrode not connected to an external electrode is arranged on the same substrate as the pair of sustaining discharge electrode so as not to pass through a center line extending in a column direction and dividing the discharge cell into two equal parts, thereby intensifying the local potential of an area of the MgO surface not influenced by the sputtering by the sustaining discharge in the address discharge, promoting the electron emission from this area, and suppressing the deterioration of the address discharge timelag.
    Type: Application
    Filed: July 18, 2008
    Publication date: March 26, 2009
    Inventors: Norihiro UEMURA, Shunichiro Nobuki, Shirun Ho, Keizo Suzuki, Masatoshi Shiiki
  • Patent number: 7482755
    Abstract: Conventionally, when a thickness of a dielectric layer is reduced without changing an electrode shape, a drive margin is reduced and stable driving cannot be performed. In a discharge cell, a display electrode comprises a projection extending in a column direction from an electrode body extending in a row direction, the projection forms a discharge gap together with an adjacent paired projection of the other display electrode, the projection includes a first projection and a second projection having two kinds of widths in a row direction, and when a ratio of widths of the second projection on the discharge gap side to the first projection on the electrode body side is assumed as Y and a thickness of the dielectric layer as X, Y?0.2·X, X?20 and Y?0.5 are satisfied.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 27, 2009
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Norihiro Uemura, Masayuki Shibata, Hideki Harada, Yoshimi Kawanami, Osamu Toyoda
  • Patent number: 7450090
    Abstract: A plasma display panel and an imaging device realize a high luminous efficiency, a long lifetime and stable driving. The plasma display panel uses a discharge-gas mixture containing at least Xe, Ne and He. A Xe proportion of the discharge-gas mixture is in a range of from 2% to 20%, a He proportion of the discharge-gas mixture is in a range of from 15% to 50%, the He proportion is greater than the Xe proportion, and a total pressure of the discharge-gas mixture is in a range of from 400 Torr to 550 Torr. A width of a voltage pulse to be applied to an electrode serving as an address electrode is 2 ?s or less.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: November 11, 2008
    Assignees: Hitachi, Ltd., Fujitsu Hitachi Plasma Display, Ltd.
    Inventors: Norihiro Uemura, Keizo Suzuki, Hiroshi Kajiyama, Yusuke Yajima, Masayuki Shibata, Yoshimi Kawanami, Koji Ohira, Ikuo Ozaki