Abstract: The present invention is directed to a semiconductor device having a non-volatile memory cell 18, and a readout circuit 102 which reads out data of the memory cell 18 DATA using a first data DATA1 obtained by sensing a first reference level REF1 for reading out the data of the memory cell 18 and a level of the memory cell 18 CORE and using a second data DATA2 obtained by sensing a second reference level REF2 for reading out the data of the memory cell 18 and the level of the memory cell 18 CORE, and to a controlling method for the same.

Abstract: The present invention is directed to a semiconductor device having a non-volatile memory cell 18, and a readout circuit 102 which reads out data of the memory cell 18 DATA using a first data DATA1 obtained by sensing a first reference level REF1 for reading out the data of the memory cell 18 and a level of the memory cell 18 CORE and using a second data DATA2 obtained by sensing a second reference level REF2 for reading out the data of the memory cell 18 and the level of the memory cell 18 CORE, and to a controlling method for the same.

Abstract: A shared memory system and an arbitrating method and system. When the processing is distributed over a plurality of CPUs (e.g., CPUA and CPUB) and if it is desired that a shared memory is used to transfer data between the CPUs, a clock CKG indicating the CPUA access timing clock is generated. A gate signal G indicating the access right to the shared memory is generated in synchronism with the clock CKG. When either of the CPUs requests the access to the shared memory, it makes the corresponding chip select signal CSA.sup.- or CSB.sup.- L-level. The access right is always directed to the CPUA and switched to the CPUB in response to the access demand from the CPUB. After one access has completed, the CPUB makes CSB.sup.- H-level. Thus, the access right is switched to the CPUA. After one access has terminated, the CPUA makes CSA.sup.- H-level. If the CPUB requests the access at this time, the access right is switched to the CPUB.