Abstract: A nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix pattern and means for sensing data stored in said memory cells, characterized in that each of said memory cells comprises a pair of symmetrical submemory cells, and the pair of said submemory cells can store logic states opposite to each other.

Abstract: A nonvolatile semiconductor memory device formed of a plurality of memory cells arranged in a matrix pattern includes a plurality of reference cells, a reference voltage supply, and differential type sensing amplifiers connected to output lines of the memory cells and to an output line of the reference cells. In one embodiment the storage capability of each memory cell is tested by comparing the cell voltage to the reference voltage by selectively connecting the reference cell output line with the sensing amplifier associated with the column containing the cell under test. A memory cell is determined to be defective when the difference between the cell voltage and the reference voltage, that is, the output of the differential sensing amplifier, is below a predetermined value.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with sense amplifier circuits at the center of each column and an intermediate output buffer having inputs connected to both sides of the column lines. The intermediate output buffer is a bistable circuit wherein the load transistors have clock voltages applied to their gates after an initial sensing period, so the initial sensing of data on the column lines is done without loads. After this initial period, the load transistors are turned on by booting capacitors. Then, transistors shunting the gates of the load devices to the sense nodes function to turn off the load device on the zero logic level side. The gates of these shunting transistors are each controlled by the voltages on the sense node on the opposite side of the bistable circuit.

Abstract: Disclosed is an address buffer circuit for use in semiconductor memories. The buffer includes a pair of cross-coupled transistors having set and reset nodes that are precharged to a predetermined level prior to sensing the input address signals. The set and reset nodes couple to a pair of load transistors that are also precharged prior to sensing. Actual sensing occurs by further charging or discharging the set and reset nodes at rates that reflect the state of the input address signal. A current sinking circuit detects the different charge or discharge rate and selectively sinks the precharge on one load transistor thereby latching the state of the input address signal.

Abstract: Disclosed is a read clock generator for use in a semiconductor memory. The read clock generator is comprised of a bistable amplifier and a differential voltage sensor. The bistable amplifier is activated during a read cycle; and it simulates the transient operation of a plurality of sense amplifiers which sense binary information stored within the memory. The differential voltage sensor couples to the bistable amplifier, and produces an output signal when the bistable amplifier stabilizes.

Abstract: A random access memory device of the MOS integrated circuit type using an array of one-transistor storage cells employs bistable sense amplifier circuits, one located in the center of each column line. The bistable circuits have current-limiting control devices in series therewith and the control devices are selected by the address circuits in a manner such that during an initial sensing period the current is low, then during a later period more current may be permitted for a higher level output. In parts of the array which are not being accessed by the current address, the increased current level is not permitted, thus reducing power dissipation.