Patents by Inventor Norihito Miyoshi

Norihito Miyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit having interconnection with improved design flexibility, and method of production
    Patent number: 5240867
    Abstract: A semiconductor integrated circuit comprises a substrate of a first semiconductor type doped by a first impurity element with a first impurity density, the first semiconductor type being one of p-type and n-type semiconductors, a conductive layer formed on a back surface of the substrate, a first layer of a second semiconductor type doped by a second impurity element different from the first impurity element and formed on a front surface of the substrate, the second semiconductor type being the other of the p-type and n-type semiconductors and the first layer having a second impurity density lower than the first impurity density, a second layer of the first semiconductor type formed on the first layer for forming circuit elements therein, a first region of the second semiconductor type extending from a top surface of the first layer and reaching a top surface of the second layer, and a second region of the first semiconductor type extending from a top surface of the substrate and reaching the top surface of s
    Type: Grant
    Filed: September 11, 1991
    Date of Patent: August 31, 1993
    Assignee: Fujitsu Limited
    Inventors: Kouichi Suzuki, Norihito Miyoshi, Makoto Yoshida, Masayuki Kokado
  • Semiconductor integrated circuit having interconnection with improved design flexibility, and method of production
    Patent number: 5065216
    Abstract: A semiconductor integrated circuit comprises a substrate of a first semiconductor type doped by a first impurity element with a first impurity density, the first semiconductor type being one of p-type and n-type semiconductors, a conductive layer formed on a back surface of the substrate, a first layer of a second semiconductor type doped by a second impurity element different from the first impurity element and formed on a front surface of the substrate, the second semiconductor type being the other of the p-type and n-type semiconductors and the first layer having a second impurity density lower than the first impurity density, a second layer of the first semiconductor type formed on the first layer for forming circuit elements therein, a first region of the second semiconductor type extending from a top surface of the first layer and reaching a top surface of the second layer, and a second region of the first semiconductor type extending from a top surface of the substrate and reaching the top surface of s
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: November 12, 1991
    Assignee: Fujitsu Ltd.
    Inventors: Kouichi Suzuki, Norihito Miyoshi, Makoto Yoshida, Masayuki Kokado