Abstract: In a pipeline computer, a store sub-instruction address is stored into a most recent address register as well as into an address buffer in response to a store request and a load sub-instruction address is supplied to a main memory in response to a load sub-instruction. When a store sub-instruction data is stored into a buffer following the storage of the store sub-instruction address into the most recent address register, the contents of the address buffer and the data buffer are transferred to a location of the main memory specified by the sub-instruction address. Main memory data is retrieved from a location specified by an associated load sub-instruction address. A match or a mismatch is detected between the address in the most recent address register and an address generated in response to a subsequent load sub-instruction.