Abstract: A communication device to be coupled to a transmission device with MC-LAG, the communication device includes a first output port coupled to an other communication device within a first route, a second output port within a second route, an iTAS device arranged in each of the first output port and the second output port, and configured to preferentially output a high priority flow, based on a set an iTAS period, a memory, and a processor coupled to the memory and configured to acquire a first iTAS period set to the iTAS device arranged in the first output port and a second iTAS period set to an iTAS device arranged in a third output port in the other communication device within the first route, and set an iTAS period of the iTAS device arranged in the second output port, based on the first and second iTAS periods.

Abstract: A packet switch includes a memory, and a processor coupled to the memory and configured to learn a pattern of a high-priority packet having a cyclicity, monitor a burst end point of the high-priority packet, based on a result of the learning, detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes, and determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.

Abstract: A packet switch includes a memory, and a processor coupled to the memory and configured to learn a pattern of a high-priority packet having a cyclicity, monitor a burst end point of the high-priority packet, based on a result of the learning, detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes, and determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.

Abstract: A packet processing device includes: a non-priority packet storage that stores the non-priority packet; a gate provided on an output side of the non-priority packet storage; plural priority packet storages that respectively store the priority packet; a distributer that guides a received priority packet to a priority packet storage corresponding to a delay time of a route through which the received priority packet is transmitted; a timing setting unit that sets different read cycles to respective priority packet storages; a read controller that reads priority packets from the plural priority packet storages according to the read cycles; and a gate controller that controls the gate according to the timings on which the read priority packets are output. When the read controller reads a first priority packet from one of the priority packet storages, the read controller reads a second priority packet from another priority packet storage.

Abstract: A packet transfer device includes a circuit configured to include a first queue to store a first packet classified into a high priority class and a second queue to store a second packet classified into a low priority class, a memory configured to store data configured to indicate possibilities of output for the first packet and the second packet for each time slot, a processor coupled to the memory and configured to control the output of the first packet and the second packet for each time slot according to the data stored in the memory, count a number of discards of the second packet within the second queue in a predetermined cycle, and change the data stored in the memory, when the number of discards is less than a first predetermined value, so as to reduce an output period of the second packet every the time slot.

Abstract: A packet processing device includes: a non-priority packet storage that stores the non-priority packet; a gate provided on an output side of the non-priority packet storage; plural priority packet storages that respectively store the priority packet; a distributer that guides a received priority packet to a priority packet storage corresponding to a delay time of a route through which the received priority packet is transmitted; a timing setting unit that sets different read cycles to respective priority packet storages; a read controller that reads priority packets from the plural priority packet storages according to the read cycles; and a gate controller that controls the gate according to the timings on which the read priority packets are output. When the read controller reads a first priority packet from one of the priority packet storages, the read controller reads a second priority packet from another priority packet storage.

Abstract: A packet transfer device includes a circuit configured to include a first queue to store a first packet classified into a high priority class and a second queue to store a second packet classified into a low priority class, a memory configured to store data configured to indicate possibilities of output for the first packet and the second packet for each time slot, a processor coupled to the memory and configured to control the output of the first packet and the second packet for each time slot according to the data stored in the memory, count a number of discards of the second packet within the second queue in a predetermined cycle, and change the data stored in the memory, when the number of discards is less than a first predetermined value, so as to reduce an output period of the second packet every the time slot.

Abstract: A communication method executed by a processor included in a relay device, the communication method includes receiving a target packet among a plurality of segmented packets generated by dividing a transmission packet, the plurality of segmented packets including a same identifier as that of the transmission packet; storing the target packet into a memory, when no error is detected from the target packet; discarding one or more packets stored in the memory and including a same identifier as that of the target packet, when an error is detected from the target packet; generating a discard request including an identifier of the transmission packet, and information requesting to discard a packet including the identifier, when the discarded one or more packets do not include a head packet among the plurality of segmented packets; and transmitting the discard request to a transmission destination to which the head packet is transmitted.

Abstract: A communication method executed by a processor included in a relay device, the communication method includes receiving a target packet among a plurality of segmented packets generated by dividing a transmission packet, the plurality of segmented packets including a same identifier as that of the transmission packet; storing the target packet into a memory, when no error is detected from the target packet; discarding one or more packets stored in the memory and including a same identifier as that of the target packet, when an error is detected from the target packet; generating a discard request including an identifier of the transmission packet, and information requesting to discard a packet including the identifier, when the discarded one or more packets do not include a head packet among the plurality of segmented packets; and transmitting the discard request to a transmission destination to which the head packet is transmitted.

Abstract: The present invention is comprised for pre-setting bandwidth control information of each user for each of the number of normal physical links which are integrated as a Link Aggregation, recognizing the number of currently normal physical links if a failure, or recovery therefrom, of a physical link which is integrated as the aforementioned Link Aggregation, and carrying out a bandwidth control, for each user traffic, corresponding to the number of the recognized normal physical links by referring to bandwidth control information of each user for each of the number of preset normal physical links, in order to prevent an occurrence of unfairness in usable bandwidth among the users even in the case of a failure occurrence in respective physical links which are logically integrated as a Link Aggregation.

Abstract: The present invention is comprised for pre-setting bandwidth control information of each user for each of the number of normal physical links which are integrated as a Link Aggregation, recognizing the number of currently normal physical links if a failure, or recovery therefrom, of a physical link which is integrated as the aforementioned Link Aggregation, and carrying out a bandwidth control, for each user traffic, corresponding to the number of the recognized normal physical links by referring to bandwidth control information of each user for each of the number of preset normal physical links, in order to prevent an occurrence of unfairness in usable bandwidth among the users even in the case of a failure occurrence in respective physical links which are logically integrated as a Link Aggregation.