Abstract: According to this invention, a base extracting electrode is formed using a polysilicon side wall self-aligned with a base region so as to reduce a collector-base parasitic capacitance of a transistor. A base layer is formed on a semiconductor substrate by a selective epitaxial method using an MBE method to obtain a high-speed operation. A high impurity-concentration region is formed on a buried layer immediately below an emitter by pedestal ion implantation to reduce a collector series resistance. In addition, a specific layer of a plurality of polysilicon layers is selectively annealed by radiation of an eximer laser to operate the transistor at high speed and to obtain a highly accurate resistor element.

Abstract: To reduce the parasitic capacitance due to the graft base area in a transistor device and to miniaturize the device, the graft base area is connected to a conductive layer to be connected to the base electrode through a minute gap of about 1,000 .ANG.. This minute gap can be formed by leaving an oxide resistant layer (1,000 .ANG.) at the side wall portion of the conductive layer of which peripheral portion is perpendicular to the surface of the base area by applying an isotropic etching technique and by removing the remaining oxide resistant layer on the basis of selective etching technique, after thermal oxidation of the device with masking the side wall portion by the remaining oxide resistant layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first region of first conductivity type in the substrate, a second region of second conductivity type in the substrate and adjacent to the first region, a third region of the first conductivity type adjacent to the second region having at least a portion on the substrate which is comprised of the same element as the substrate and oxygen, the band gap energy of the portion being larger than that of the second region and means for transporting majority carriers in the first region to the third region.