Patents by Inventor Norikazu Ouchi

Norikazu Ouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5856228
    Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: January 5, 1999
    Assignee: Sony Corporation
    Inventors: Hiroyuki Miwa, Shigeru Kanematsu, Takayuki Gomi, Hiroaki Anmo, Takashi Noguchi, Katsuyuki Kato, Hirokazu Ejiri, Norikazu Ouchi
  • Patent number: 5643806
    Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 1, 1997
    Assignee: Sony Corporation
    Inventors: Hiroyuki Miwa, Shigeru Kanematsu, Takayuki Gomi, Hiroaki Anmo, Takashi Noguchi, Katsuyuki Kato, Hirokazu Ejiri, Norikazu Ouchi
  • Patent number: 5541124
    Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 30, 1996
    Assignee: Sony Corporation
    Inventors: Hiroyuki Miwa, Shigeru Kanematsu, Takayuki Gomi, Hiroaki Anmo, Takashi Noguchi, Katsuyuki Kato, Hirokazu Ejiri, Norikazu Ouchi
  • Patent number: 5352624
    Abstract: A lateral bipolar transistor including a transistor forming region provided on an insulating substrate; a first impurity diffusing region provided on the insulating substrate on one side of the transistor forming region; an emitter region formed in a first portion of the transistor forming region adjacent to the first impurity diffusing region, the emitter region being formed by diffusing a first conduction type of impurity from the first impurity diffusing region into the first portion of the transistor forming region; a base region formed in a second portion of the transistor forming region adjacent to the emitter region, the base region being formed by diffusing a second conduction type of impurity from the first impurity diffusing region into the second portion of the transistor forming region; and a collector region formed in a third portion of the transistor forming region adjacent to the base region. Accordingly, a base width can be reduced, and a dimensional accuracy of the base width can be improved.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: October 4, 1994
    Assignee: Sony Corporation
    Inventors: Hiroyuki Miwa, Norikazu Ouchi
  • Patent number: 4591398
    Abstract: The present invention is to provide a method for manufacturing a semiconductor device of high efficiency and high integration density. The method for manufacturing a semiconductor device comprises the steps of forming semiconductive layers (30), (31) and (31') having on the surface thereof a concave portion, forming a nitride layer (35) within the concave portions forming with the nitride layer (35) as a mask an oxide layer (39) on the surface of the semiconductive layer (30), removing said nitride layer (35) and introducing an impurity into the semiconductive layers (31) and (31') with the oxide layer (39) as a mask. In accordance therewith, the elements can be made finer and hence the method of this invention is suitable for manufacturing an IC device high in efficiency and high in integration density.
    Type: Grant
    Filed: January 25, 1985
    Date of Patent: May 27, 1986
    Assignee: Sony Corporation
    Inventors: Norikazu Ouchi, Akio Kayanuma, Katsuaki Asano