Patents by Inventor Norikazu Ozaki

Norikazu Ozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240064907
    Abstract: An object is to provide a circuit board that includes a built-in semiconductor device and has a configuration that prevents cracking and has excellent reliability in operation over a wide temperature range. As a solution, a circuit board (10A) has a configuration in which a first insulating substrate (1) is laminated on a second insulating substrate (2) while interposing a first adhesive layer (7a), and a semiconductor device (9) is embedded in an embedment portion (1c) formed in the first insulating substrate (1).
    Type: Application
    Filed: February 22, 2022
    Publication date: February 22, 2024
    Applicant: FICT LIMITED
    Inventors: Taiji Sakai, Kenji Iida, Norikazu Ozaki, Kenji Takano, Takashi Nakagawa, Takayuki Inaba, Tetsuro Miyagawa, Akira Yajima, Shin Hirano, Kota Aoi, Yoichi Abe, Mio Emura
  • Publication number: 20230180398
    Abstract: A circuit board includes a plurality of first insulating base materials and a plurality of second insulating base materials that are alternately laminated, a first metal layer being formed into a pattern shape on a first surface of the first insulating base material, and a second metal layer being formed into a pattern shape on a second surface of the first insulating base material. The first metal layer is formed into a trapezoidal shape that is large in diameter on a first surface side of the first insulating base material. The second metal layer is formed into a trapezoidal shape that is large in diameter on a second surface side of the first insulating base material. The first metal layers and the second metal layers are laminated in such a manner that the trapezoidal shapes are alternately oriented.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 8, 2023
    Applicant: FICT LIMITED
    Inventors: Kenji Iida, Norikazu Ozaki, Taiji Sakai, Takashi Nakagawa, Kenji Takano, Takayuki Inaba, Akira Yajima, Shin Hirano, Kota Aoi, Tetsuro Miyagawa
  • Publication number: 20220312595
    Abstract: A substrate that enables increasing an allowable current value of a current path in a thickness direction of the substrate and narrowing spaces between multiple current paths, and the like are provided. To solve this subject, a substrate includes a sheet-shaped first base material (1) having a penetrating hole (1B) in the thickness direction and includes a second base material (2) fitted into the penetrating hole (1B). The second base material (2) includes multiple metal bodies (2B). The metal bodies (2B) penetrate in the thickness direction of the first base material (1) in a state of having an end exposed at each of a first surface and a second surface of the second base material (2) that face each other in the thickness direction.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 29, 2022
    Applicant: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Hiroshi Nakano, Norikazu Ozaki
  • Patent number: 10009998
    Abstract: A first through hole is formed in a base, a conductive layer covering an inner wall side surface of the first through hole is formed, a columnar electric conductor having a Vickers hardness of a value in a range of 30 Hv or more and 400 Hv or less is inserted into the first through hole formed with the conductive layer, pressure is applied in a vertical direction to the columnar electric conductor, and a second through hole is formed in the columnar electric conductor.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 26, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Norikazu Ozaki, Hiroshi Miyao, Satoru Hasegawa
  • Publication number: 20180160547
    Abstract: A first through hole is formed in a base, a conductive layer covering an inner wall side surface of the first through hole is formed, a columnar electric conductor having a Vickers hardness of a value in a range of 30 Hv or more and 400 Hv or less is inserted into the first through hole formed with the conductive layer, pressure is applied in a vertical direction to the columnar electric conductor, and a second through hole is formed in the columnar electric conductor.
    Type: Application
    Filed: November 8, 2017
    Publication date: June 7, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu Ozaki, Hiroshi MIYAO, Satoru HASEGAWA
  • Patent number: 8642894
    Abstract: Provided is a circuit board including a resin base, and a resistance element formed above the resin base. The resistance element includes a resistance pattern including an electrode portion and an extending portion, and an electrode formed on the electrode portion of the resistance pattern and including a foot portion reduced in thickness toward the extending portion.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: February 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Abe, Norikazu Ozaki
  • Patent number: 8186052
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: May 29, 2012
    Assignee: Fujitsu Limited
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: 8153908
    Abstract: The circuit board is capable of tightly bonding a cable layer on a base member even if thermal expansion coefficients of the base member and the cable layer are significantly different. The circuit board comprises: the base member; and the cable layer being laminated on the base member with anchor patterns, which are electrically conductive layers formed on a surface of the base member.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: April 10, 2012
    Assignee: Fujitsu Limited
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: 8151456
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: April 10, 2012
    Assignee: Fujitsu Limited
    Inventors: Yasutomo Maehara, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: 8035037
    Abstract: The core substrate is capable of securely preventing short circuit between an electrically conductive core section and a plated through-hole section. The core substrate comprises: an electrically conductive core section having a pilot hole, through which a plated through-hole section is formed; electrically conductive layers coating the inner face of the pilot hole and a surface of the core section; a gas purging hole being formed in the conductive layer coating the surface of the core section; an insulating material filling a space between the inner face of the pilot hole and an outer circumferential face of the plated through-hole section; and cable layers being laminated on both side faces of the core section.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 11, 2011
    Assignee: Fujitsu Limited
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20100193225
    Abstract: Provided is a circuit board including a resin base, and a resistance element formed above the resin base. The resistance element includes a resistance pattern including an electrode portion and an extending portion, and an electrode formed on the electrode portion of the resistance pattern and including a foot portion reduced in thickness toward the extending portion.
    Type: Application
    Filed: January 19, 2010
    Publication date: August 5, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Abe, Norikazu Ozaki
  • Publication number: 20100018758
    Abstract: A printed wiring board which includes a core substrate and a plurality of buildup layer. The core substrate contains carbon fiber. The plurality of buildup layers is stacked on the core substrate. The buildup layer includes an insulating layer and a conductive wiring layer. The insulating layer contains a resin material having a glass fiber cloth embedded therein.
    Type: Application
    Filed: June 18, 2009
    Publication date: January 28, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki Yoshimura, Norikazu Ozaki, Kenji Iida, Tomoyuki Abe
  • Publication number: 20100018762
    Abstract: A printed circuit board includes a first insulation layer that is formed of a resin material into which fiber cloth is embedded. A second insulation layer is formed of a resin material, and is stacked on a front surface of the first insulation layer on which a heating process has been performed. A conductive land is formed on a front surface of the second insulation layer. A via is provided in a through hole penetrating through the first insulation layer and the second insulation layer. The through hole is filled with a conductive material, and the via is connected to the conductive land.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 28, 2010
    Inventors: Hideaki YOSHIMURA, Norikazu OZAKI, Kenji IIDA, Tomoyuki ABE
  • Publication number: 20090095511
    Abstract: The circuit board is capable of tightly bonding a cable layer on a base member even if thermal expansion coefficients of the base member and the cable layer are significantly different. The circuit board comprises: the base member; and the cable layer being laminated on the base member with anchor patterns, which are electrically conductive layers formed on a surface of the base member.
    Type: Application
    Filed: July 15, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kenji IIDA, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090095509
    Abstract: In the core substrate, short circuit between an electrically conductive core section and a plated through-hole section can be securely prevented and cables can be formed in a high dense state. The core substrate comprises: the electrically conductive core section having a pilot hole, through which the plated through-hole section is formed; cable layers being respectively laminated on the both side faces of the core section; a plated layer coating an inner face of the pilot hole; and an insulating material filling a space between the plated layer and an outer circumferential face of the plated through-hole section.
    Type: Application
    Filed: August 8, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Shin Hirano, Kenji Iida, Yasutomo Maehara, Tomoyuki Abe, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090094825
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.
    Type: Application
    Filed: July 18, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Yasutomo MAEHARA, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Publication number: 20090094824
    Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.
    Type: Application
    Filed: July 15, 2008
    Publication date: April 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
  • Patent number: D697093
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 7, 2014
    Assignee: Panasonic Corporation
    Inventor: Norikazu Ozaki
  • Patent number: D732087
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 16, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Norikazu Ozaki, Ricardo Kolb Filho
  • Patent number: D765743
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: September 6, 2016
    Assignee: PANASONIC CORPORATION
    Inventor: Norikazu Ozaki