Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: The wire length of an LSI is estimated from a netlist describing connection information of the LSI and a cell library storing information as to cells used in the LSI design, with performing no rough placement and rough wiring by a layout system. Information necessary for wire length estimation is extracted from the netlist and the cell library. A net basic wire length is determined for each fan-out. In a net wire length estimating step, a net wire length for each fan-out is estimated by making reference to the determined net basic wire length and taking into account net expansion due to the cell distribution in a cell placement. Additionally, taking into account a terminal distribution and the aspect ratio of an estimation-target block, a correction on the estimated net wire length is made. From the corrected net wire length, the total wire length of the estimation-target block is estimated.