Patents by Inventor Noriko Omori
Noriko Omori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220068614Abstract: The present invention relates to a semiconductor manufacturing member including a silicon carbide-containing boron carbide film at least on a surface thereof, in which the silicon carbide-containing boron carbide film has a content of silicon carbide of 5 wt % or more and 18 wt % or less and a balance being boron carbide.Type: ApplicationFiled: August 23, 2021Publication date: March 3, 2022Inventors: Masahiko ICHISHIMA, Hiroshi OISHI, Noriko OMORI, Akira MIYAZAKI, Masahiro KUBOTA, Jun KOMIYAMA
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Patent number: 10559679Abstract: There is provided a nitride semiconductor epitaxial substrate having a channel layer, a spacer layer, and an electron supply layer that are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1-aN (0<a<0.5). The electron supply layer is AlxlnyGa1-x-yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less.Type: GrantFiled: August 17, 2018Date of Patent: February 11, 2020Assignee: COORSTEK KKInventors: Hiroshi Oishi, Noriko Omori, Yoshihisa Abe
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Publication number: 20190074369Abstract: There is provided a nitride semiconductor epitaxial substrate having a spacer structure capable of obtaining characteristics unprecedented in the prior art. In the nitride semiconductor epitaxial substrate of the present invention, a channel layer, a spacer layer, and an electron supply layer are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1?aN (0<a<0.5). The electron supply layer is AlxInyGa1?x?yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less. Thus, adverse effects due to the existence of a conventional spacer layer are suitably suppressed.Type: ApplicationFiled: August 17, 2018Publication date: March 7, 2019Applicant: CoorsTek KKInventors: Hiroshi OISHI, Noriko OMORI, Yoshihisa ABE
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Patent number: 10068858Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.Type: GrantFiled: October 4, 2016Date of Patent: September 4, 2018Assignee: COORSTEK KKInventors: Yoshihisa Abe, Kenichi Eriguchi, Noriko Omori, Hiroshi Oishi, Jun Komiyama
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Publication number: 20180151714Abstract: Provided is a nitride semiconductor substrate which improves electron mobility and reduce a series resistance component of a transistor. In the nitride semiconductor substrate, an electron transit layer, an intermediate layer, and an electron supply layer are laminated in this order. The electron transit layer includes a nitride semiconductor of a first group 13 element. The intermediate layer and the electron supply layer each include a nitride semiconductor of the first group 13 element and a second group 13 element. The nitride semiconductor substrate has a profile in which an atomic ratio of the second group 13 element to a total of the first group 13 element and the second group 13 element increases in the thickness direction of the intermediate layer from an interface between the electron transit layer and the intermediate layer, and the atomic ratio decreases after a maximum peak value is obtained in the intermediate layer.Type: ApplicationFiled: November 17, 2017Publication date: May 31, 2018Applicant: CoorsTek KKInventors: Noriko OMORI, Hiroshi OISHI, Yoshihisa ABE, Jun KOMIYAMA
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Patent number: 9748344Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.Type: GrantFiled: July 6, 2016Date of Patent: August 29, 2017Assignee: COORSTEK KKInventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
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Publication number: 20170110414Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.Type: ApplicationFiled: October 4, 2016Publication date: April 20, 2017Applicant: COORSTEK KKInventors: Yoshihisa ABE, Kenichi ERIGUCHI, Noriko OMORI, Hiroshi OISHI, Jun KOMIYAMA
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Publication number: 20170011919Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.Type: ApplicationFiled: July 6, 2016Publication date: January 12, 2017Applicant: CoorsTek KKInventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
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Patent number: 9530846Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.Type: GrantFiled: March 29, 2016Date of Patent: December 27, 2016Assignee: CoorsTek KKInventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
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Publication number: 20160293710Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.Type: ApplicationFiled: March 29, 2016Publication date: October 6, 2016Applicant: CoorsTek KKInventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi