Abstract: It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a plurality of signal wirings having an equal width which is disposed in parallel with each other at a regular interval, and at least two of the signal wirings which are adjacent to each other are electrically connected to each other.

Abstract: In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a predetermined range, while a logic gate in the circuit block is selected when the amount of noise is out of the predetermined range and a bypass condenser is added to the selected logic gate. Therefore, a bypass condenser having a required capacitance can be added in the vicinity of a noise source in the circuit block, whereby the noise can be reliably restricted to the predetermined range.

Abstract: It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a plurality of signal wirings having an equal width which is disposed in parallel with each other at a regular interval, and at least two of the signal wirings which are adjacent to each other are electrically connected to each other.

Abstract: In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a predetermined range, while a logic gate in the circuit block is selected when the amount of noise is out of the predetermined range and a bypass condenser is added to the selected logic gate. Therefore, a bypass condenser having a required capacitance can be added in the vicinity of a noise source in the circuit block, whereby the noise can be reliably restricted to the predetermined range.

Abstract: In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a predetermined range, while a logic gate in the circuit block is selected when the amount of noise is out of the predetermined range and a bypass condenser is added to the selected logic gate. Therefore, a bypass condenser having a required capacitance can be added in the vicinity of a noise source in the circuit block, whereby the noise can be reliably restricted to the predetermined range.

Abstract: A layout symmetry constraint checking method and apparatus for efficiently checking a layout symmetry constraint is provided. The layout symmetry constraint is checked by performing a first checking step of checking, for example, a match between shapes of a symmetrical element pair for input layout data, a second checking step of checking whether or not a relative positional relationship between elements is contradictory to the layout symmetry constraint, and a third checking step of checking whether or not a geometric placement of the elements satisfies the layout symmetry constraint. When an error occurs in each of the checking steps, a cause for the error is specified and presented to the designer, thereby achieving efficient layout design.

Abstract: In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are-inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a predetermined range, while a logic gate in the circuit block is selected when the amount of noise is out of the predetermined range and a bypass condenser is added to the selected logic gate. Therefore, a bypass condenser having a required capacitance can be added in the vicinity of a noise source in the circuit block, whereby the noise can be reliably restricted to the predetermined range.

Abstract: In a semiconductor integrated circuit device, at least one I/O cell can be disposed in a desired position within a chip. The semiconductor integrated circuit device includes an ESD protection circuit separated from the I/O cell and disposed in an ESD protection circuit region provided in a peripheral portion of the chip; the I/O cell disposed closer to the center of the chip than the ESD protection circuit region; and a wire for connecting the I/O cell to the ESD protection circuit.

Abstract: Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction reaction a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.

Abstract: First, initial routing is performed on a net. If a design rule error exists in a wire already routed as a result of the initial routing, the wire already routed, causing the design rule error, is removed. Next, if the wire already routed and removed is a wire interconnecting a movable terminal, freely placeable within a predetermined region, to another terminal, then the movable terminal is displaced within the predetermined region and the removed wire is re-routed such that the displaced movable terminal is interconnected to the other terminal. Accordingly, the movable terminal can be located at an appropriate position within the predetermined region in accordance with the situation of surrounding wires. As a result, routing results of a higher density can be obtained.

Abstract: Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction on a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.

Abstract: In a semiconductor integrated circuit device, at least one I/O cell can be disposed in a desired position within a chip. The semiconductor integrated circuit device includes an ESD protection circuit separated from the I/O cell and disposed in an ESD protection circuit region provided in a peripheral portion of the chip; the I/O cell disposed closer to the center of the chip than the ESD protection circuit region; and a wire for connecting the I/O cell to the ESD protection circuit.

Abstract: In designing a layout for a deep-submicron semiconductor integrated circuit, a violational wire involving a violation of the delay limitation is extracted based on information representing a layout result obtained in a layout step. In order to extend a wire spacing between such an extracted wire and its neighboring wire to above a predetermined wire spacing, the neighboring wire is subjected to parallel displacement. If such a parallel displacement causes a distance of separation between the parallelly-displaced wire and its neighboring component to fall below a predetermined distance of separation, the component in question is shifted in order of extending the separation distance. Accordingly, even if the delay time of wire is dominant in comparison with that of element in regard to the signal propagation delay time, violations of the delay limitation occurring when the signal propagation delay time is less than a predetermined delay time can be canceled by a less number of steps.

Abstract: Elements such as a transistor having a terminal corresponding to a wire junction are abstracted by using rectangles, and a spit penetrating these rectangles is introduced in a layout area where the rectangles are disposed. On the spit, a wire junction for allocating a wire is provided. The terminals of the rectangles corresponding to the wire junctions and the wire junctions on the spit are set as net targets, and connection information on these net targets is generated. A scan line for scanning the layout area from its left end to its right end and a front for tracing the net targets are introduced. While conducting rightward scanning by the scan line, the front is proceeded from one net target to the other net target. The trace of the front is provided as a wire element.

Abstract: To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area.By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.