Abstract: An image forming apparatus transmits job histories that satisfy monitoring conditions to a storage service and stores job histories that do not satisfy the conditions in an information processing apparatus. When a job execution user is added to the monitoring conditions, the job history information corresponding to the added job execution user among the job histories stored in the information processing apparatus is transmitted to the storage service. The storage service manages the job history that satisfies the monitoring condition received from the image forming apparatus and notifies the administrator. When the job history information that does not meet the monitoring conditions is received, the information is notified to the administrator.

Abstract: A system includes a first cloud print service and a second cloud print service, the first cloud print service connected with a client terminal via a network and the second cloud print service connected with an image forming apparatus via the network. The first cloud print service stores print job data received from the client terminal in one or more first memories, requires the second cloud print service to issue a job code of the print job data, associates the job code issued by the second cloud print service with the print job data, and transmits the stored print job data to the second cloud print service when receiving information indicating the stored print job data from the second cloud print service.

Abstract: An image forming apparatus transmits job histories that satisfy monitoring conditions to a storage service and stores job histories that do not satisfy the conditions in an information processing apparatus. When a job execution user is added to the monitoring conditions, the job history information corresponding to the added job execution user among the job histories stored in the information processing apparatus is transmitted to the storage service. The storage service manages the job history that satisfies the monitoring condition received from the image forming apparatus and notifies the administrator. When the job history information that does not meet the monitoring conditions is received, the information is notified to the administrator.

Abstract: A cloud print system connected to an image forming apparatus via a network comprises one or more memories storing a set of instructions and one or more processors that execute the set of instructions to store a print job received from other cloud print system and information indicating the other cloud print system, transmit the stored print job to the image forming apparatus in response to a request from the image forming apparatus, receive information of a execution result of the transmitted print job from the image forming apparatus, and transmit the received information of the execution result to the other cloud print system by using the information indicating the other cloud print system.

Abstract: A system includes a first cloud print service and a second cloud print service, the first cloud print service connected with a client terminal via a network and the second cloud print service connected with an image forming apparatus via the network. The first cloud print service stores print job data received from the client terminal in one or more first memories, requires the second cloud print service to issue a job code of the print job data, associates the job code issued by the second cloud print service with the print job data, and transmits the stored print job data to the second cloud print service when receiving information indicating the stored print job data from the second cloud print service.

Abstract: An arithmetic processing apparatus includes an arithmetic circuit configured to perform an arithmetic operation on data having a first data width and perform an instruction in parallel on each element of data having a second data width, and a cache memory configured to store data, wherein the cache memory includes a tag circuit storing tags for respective ways, a data circuit storing data for the respective ways, a determination circuit that determines a type of an instruction with respect to whether data accessed by the instruction has the first data width or the second data width, and a control circuit that performs either a first pipeline operation where the tag circuit and the data circuit are accessed in parallel or a second pipeline operation where the data circuit is accessed in accordance with a tag result after accessing the tag circuit, based on a result determined by the determination circuit.

Abstract: An arithmetic processing apparatus includes an arithmetic circuit configured to perform an arithmetic operation on data having a first data width and perform an instruction in parallel on each element of data having a second data width, and a cache memory configured to store data, wherein the cache memory includes a tag circuit storing tags for respective ways, a data circuit storing data for the respective ways, a determination circuit that determines a type of an instruction with respect to whether data accessed by the instruction has the first data width or the second data width, and a control circuit that performs either a first pipeline operation where the tag circuit and the data circuit are accessed in parallel or a second pipeline operation where the data circuit is accessed in accordance with a tag result after accessing the tag circuit, based on a result determined by the determination circuit.

Abstract: An image forming apparatus is provided which stops, in a case where a license is determined to be invalid, periodic transmission of a state notification to a processing server until the license is determined to be valid thereafter. Further, the image forming apparatus does not output a job history that is recorded while the license is invalid to the processing server. The image forming apparatus stops recording a job history in response to the image processing apparatus being unregistered from the processing server.

Abstract: An arithmetic processing device includes a memory access request issuance unit and a cache including a cache memory for tags and data and a move-in buffer control unit for issuing a move-in request for data on the memory access request when a cache miss occurs. The move-in buffer control unit, when the cache miss occurs, determines to acquire a move-in buffer and issue the move-in request when the memory access request has the same index as an index of any move-in request registered in the move-in buffer and the number of move-in requests of the same index registered in the move-in buffer is less than the number of ways, and determines not to acquire the move-in buffer and does not issue the move-in request when the memory access request has the same index and the number of the move-in requests of the same index reaches the number of the ways.

Abstract: A processor includes a cache memory, an issuing unit that issues, with respect to all element data as a processing object of a load instruction, a cache request to the cache memory for each of a plurality of groups which are divided to include element data, a comparing unit that compares addresses of the element data as the processing object of the load instruction, and determines whether element data in a same group are simultaneously accessible, and a control unit that accesses the cache memory according to the cache request registered in a load queue registering one or more cache requests issued from the issuing unit. The control unit processes by one access whole element data determined to be simultaneously accessible by the comparing unit.

Abstract: An arithmetic processing unit includes a cache including a cache memory for storing states of data and data in a block at an index of the memory access request, a move-in buffer control unit that issues a move-in request when cache miss, and move-in buffers for registering the move-in request. The move-in buffer control unit, in response to cache miss, (a) secures a vacant move-in buffer when the vacant move-in buffer exists, (b) issues a move-in request when a move-in request having a same index as the memory access request is not registered in the move-in buffers, (c) issues the move-in request when the move-in request having the same index is registered in the move-in buffers and all ways are not used by the move-in request having the same index in the move-in buffers, and (d) releases the secured move-in buffer when all the ways are used.

Abstract: An image forming apparatus is provided which stops, in a case where a license is determined to be invalid, periodic transmission of a state notification to a processing server until the license is determined to be valid thereafter. Further, the image forming apparatus does not output a job history that is recorded while the license is invalid to the processing server. The image forming apparatus stops recording a job history in response to the image processing apparatus being unregistered from the processing server.

Abstract: An arithmetic processing unit includes a cache including a cache memory for storing states of data and data in a block at an index of the memory access request, a move-in buffer control unit that issues a move-in request when cache miss, and move-in buffers for registering the move-in request. The move-in buffer control unit, in response to cache miss, (a) secures a vacant move-in buffer when the vacant move-in buffer exists, (b) issues a move-in request when a move-in request having a same index as the memory access request is not registered in the move-in buffers, (c) issues the move-in request when the move-in request having the same index is registered in the move-in buffers and all ways are not used by the move-in request having the same index in the move-in buffers, and (d) releases the secured move-in buffer when all the ways are used.

Abstract: An arithmetic processing device includes a memory access request issuance unit and a cache including a cache memory for tags and data and a move-in buffer control unit for issuing a move-in request for data on the memory access request when a cache miss occurs. The move-in buffer control unit, when the cache miss occurs, determines to acquire a move-in buffer and issue the move-in request when the memory access request has the same index as an index of any move-in request registered in the move-in buffer and the number of move-in requests of the same index registered in the move-in buffer is less than the number of ways, and determines not to acquire the move-in buffer and does not issue the move-in request when the memory access request has the same index and the number of the move-in requests of the same index reaches the number of the ways.

Abstract: An arithmetic processing device includes: an instruction control circuit; primary cache circuit that includes a primary cache memory and a first buffer; and a secondary cache memory. The primary cache circuit is configured to, when a first instruction for executing processing to register data of a cache line in the secondary cache memory without the occurrence of an access to the main memory, is issued from the instruction control circuit and when data corresponding to a first address designated as an access target in the first instruction is not stored in the primary cache memory, store the first address in the first buffer and issue the first instruction to the secondary cache memory.

Abstract: A processor includes a cache memory, an issuing unit that issues, with respect to all element data as a processing object of a load instruction, a cache request to the cache memory for each of a plurality of groups which are divided to include element data, a comparing unit that compares addresses of the element data as the processing object of the load instruction, and determines whether element data in a same group are simultaneously accessible, and a control unit that accesses the cache memory according to the cache request registered in a load queue registering one or more cache requests issued from the issuing unit. The control unit processes by one access whole element data determined to be simultaneously accessible by the comparing unit.

Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.

Abstract: A job history processing server issues second agent information for use of when first agent information cannot be acquired from an agent management server. Then, the job history processing server exports, as incomplete information, data received from a collection agent together with the issued second agent information.

Abstract: A job history processing server issues second agent information for use of when first agent information cannot be acquired from an agent management server. Then, the job history processing server exports, as incomplete information, data received from a collection agent together with the issued second agent information.

Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.