Patents by Inventor Norimasa Yafune

Norimasa Yafune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8653561
    Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Katsushi Akita, Yoshiyuki Yamamoto, Masaaki Kuzuhara, Norimasa Yafune
  • Publication number: 20110278647
    Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively.
    Type: Application
    Filed: March 1, 2011
    Publication date: November 17, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Katsushi AKITA, Yoshiyuki YAMAMOTO, Masaaki KUZUHARA, Norimasa YAFUNE
  • Patent number: 8004022
    Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: August 23, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Norimasa Yafune, John Kevin Twynam
  • Patent number: 7759760
    Abstract: A semiconductor switching element, wherein on a semiconductor layer formed on a substrate, or on a semiconductor substrate, a source electrode and a drain electrode are disposed at a predetermined interval in a direction along a surface of the substrate; and a second gate electrode is provided between the source electrode and the drain electrode, the second gate electrode is electrically connected with the source electrode and structured with two types of electrode material layers having Schottky barriers of different heights from each other.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 20, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Norimasa Yafune, John Kevin Twynam
  • Publication number: 20090206373
    Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.
    Type: Application
    Filed: January 6, 2009
    Publication date: August 20, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Norimasa YAFUNE, John Kevin Twynam
  • Publication number: 20080006898
    Abstract: A semiconductor switching element, wherein on a semiconductor layer formed on a substrate, or on a semiconductor substrate, a source electrode and a drain electrode are disposed at a predetermined interval in a direction along a surface of the substrate; and a second gate electrode is provided between the source electrode and the drain electrode, the second gate electrode is electrically connected with the source electrode and structured with two types of electrode material layers having Schottky barriers of different heights from each other.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 10, 2008
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Norimasa Yafune, John Kevin Twynam