Abstract: An information processor is provided with a plurality of ALU chips under control of a microprogram and an ALU control circuit for controlling the ALU chips. The ALU control circuit responds to data bus information given thereto to select an ALU chip from which flag data is outputted. The ALU control circuit controls the ALU chip specified by the data bus information to operate it. When a carry is produced in the selected ALU chip, a carry generator is so controlled to produce a given carry signal toward a given ALU chip.

Abstract: An information processor is comprised of a plurality of circuits each of which is controlled by firmware and connected to a common bus and has a contention circuit for the bus. An arithmetic control unit for controlling the execution of the firmware is provided with a timing control circuit. When the arithmetic control unit is going to issue a bus use request or has issued the request of when it is issuing an interrupt inhibit instruction or interrupts its operation, another unit connecting to the common bus seizes the bus and interrupts the arithmetic control unit. In such a case, the timing control circuit causes the execution timing of the arithmetic control unit to be in a wait state and accepts the interrupt.