Patents by Inventor Norinaga Arai

Norinaga Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050250254
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Application
    Filed: July 12, 2005
    Publication date: November 10, 2005
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Patent number: 6946306
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: September 20, 2005
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Publication number: 20050064612
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Application
    Filed: November 9, 2004
    Publication date: March 24, 2005
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Patent number: 6852553
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Publication number: 20030003622
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Application
    Filed: May 3, 2002
    Publication date: January 2, 2003
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Patent number: 6441484
    Abstract: A semiconductor device comprises: a first semiconductor chip having a control circuit; a plurality of second semiconductor chips whose operation is controlled by the control circuit; and a resin sealing body for sealing the first semiconductor chip and the plurality of second semiconductor chips, wherein: the first semiconductor chip is arranged in the central portion of the resin sealing body; and the plurality of second semiconductor chips are arranged on a periphery of the first semiconductor chip. A fuse element is further arranged outside the plurality of second semiconductor chips.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: August 27, 2002
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Kenji Koyama, Norinaga Arai, Akio Mikami, Mamoru Iizuka
  • Publication number: 20010048148
    Abstract: A semiconductor device comprises: a first semiconductor chip having a control circuit; a plurality of second semiconductor chips whose operation is controlled by the control circuit; and a resin sealing body for sealing the first semiconductor chip and the plurality of second semiconductor chips, wherein: the first semiconductor chip is arranged in the central portion of the resin sealing body; and the plurality of second semiconductor chips are arranged on a periphery of the first semiconductor chip. A fuse element is further arranged outside the plurality of second semiconductor chips.
    Type: Application
    Filed: May 18, 2001
    Publication date: December 6, 2001
    Inventors: Kenji Koyama, Norinaga Arai, Akio Mikami, Mamoru Iizuka