Abstract: The present invention relates to a Bi-CMOS.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises:1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate;2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate;3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and4.

Abstract: A semiconductor IC device in which an N-type semiconductor layer is formed in a P-type semiconductor substrate; the N-type layer is divided by a P.sup.+ -type insulation region into plural island regions; and an IIL is formed in a first island region while an NPN transistor is formed in a second island region, wherein an N-type up-diffused layer is formed from the bottom of the first island region up while an N-type well region is formed from the surface of the first island region down, and N.sup.+ -type buried layers are formed near the bottoms of the first and the second island region.

Abstract: A method of producing an MIS structure having self-alignment construction, wherein an insulating film is formed on the surface of a semiconductor substrate, a semiconductor layer is formed on a selected area of the insulating film, parts of the insulating film are etched using the semiconductor layer as a mask, and the surface of the semiconductor layer is etched in such manner that the underlying insulating film may not be etched, whereby the marginal portion of the semiconductor layer which otherwise projects laterally beyond the underlying insulating film is caused to recede.