Abstract: According to one embodiment, a memory system includes a first memory, a second memory, and a processor. The second memory stores first management information and second management information. The first management information has an information that associates a logical address with a physical address. The second management information has an information which has a volume of valid data in each block included in the first memory. The controller updates the first management information and the second management information. When saving a differential data in the first memory, the controller stores the differential data and the second management information in one page of the first memory. The differential data is a difference between before and after update of the first management information. When restoring the second management information, the controller loads to the second memory the second management information stored in the first memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory.

Abstract: According to an embodiment, a controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines.

Abstract: According to one embodiment, when loading of reverse lookup information from a nonvolatile first memory to a randomly accessible second memory has failed, a controller determines whether data at a first physical address is valid or invalid by using lookup information loaded from the first memory to the second memory.

Abstract: According to one embodiment, a controller registers first information to a first management table, and manage the first information, the first information being management information of data buffered in the buffer memory. When the data buffered in the buffer memory is flushed to the nonvolatile memory, the controller releases, from the first management table, the first information of the flushed data, and registers, to a second management table, and manages, the first information of the flushed data.

Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.