Patents by Inventor Norio Fujita
Norio Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12131212Abstract: A reader includes: a transmission device that repeatedly transmits, at a cycle corresponding to the code length of a prescribed code string, an electromagnetic wave that is phase-adjusted with the prescribed code string; a reception device that receives the reflected wave from the object to be identified, cyclically overlaps a reception signal relating to the reflected wave at the cycle of the code length, and calculates the correlation value of the overlapped result and the prescribed code string; and a control device that controls the transmission device and varies the transmission frequency of the electromagnetic wave in a steplike manner to perform a frequency sweep within a prescribed frequency band, controls the reception device, causing the reception device to calculate the correlation value for each transmission frequency, and specifies the attributes of the object to be identified on the basis of the correlation value for each transmission frequency.Type: GrantFiled: April 2, 2021Date of Patent: October 29, 2024Assignees: KONICA MINOLTA, INC., GIT JAPAN INCORPORATEDInventors: Taketo Namikawa, Hirokazu Nakayama, Norio Fujita
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Publication number: 20230222298Abstract: A reader includes: a transmission device that repeatedly transmits, at a cycle corresponding to the code length of a prescribed code string, an electromagnetic wave that is phase-adjusted with the prescribed code string; a reception device that receives the reflected wave from the object to be identified, cyclically overlaps a reception signal relating to the reflected wave at the cycle of the code length, and calculates the correlation value of the overlapped result and the prescribed code string; and a control device that controls the transmission device and varies the transmission frequency of the electromagnetic wave in a steplike manner to perform a frequency sweep within a prescribed frequency band, controls the reception device, causing the reception device to calculate the correlation value for each transmission frequency, and specifies the attributes of the object to be identified on the basis of the correlation value for each transmission frequency.Type: ApplicationFiled: April 2, 2021Publication date: July 13, 2023Inventors: Taketo NAMIKAWA, Hirokazu NAKAYAMA, Norio FUJITA
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Patent number: 10223303Abstract: A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.Type: GrantFiled: July 20, 2016Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Patent number: 10169263Abstract: A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.Type: GrantFiled: July 20, 2016Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Patent number: 9710375Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.Type: GrantFiled: May 28, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventor: Norio Fujita
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Patent number: 9710378Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.Type: GrantFiled: November 9, 2016Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventor: Norio Fujita
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Publication number: 20170052888Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.Type: ApplicationFiled: November 9, 2016Publication date: February 23, 2017Inventor: Norio Fujita
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Patent number: 9514084Abstract: The present invention provides a computer system including a CPU with an L2 cache, a bus master device and a bus slave device. They are connected via a system bus to communicate with each other. The computer system 100 includes: a transaction monitor 60 for monitoring first transaction states TrC1-TrCn between a CPU 20 and an L2 cache 25, and second transaction states from TrB0 to TrBn between a system bus 10 and the L2 cache 25, between the system bus 10 and a bus master device 30 or between the system bus 10 and bus slave devices 40, 42; and a clock generator 70 able to change the frequency FreqC1-FreqS2 of the clock of the CPU 20, the system bus 10, and the bus slave devices 40, 42 according to the first transaction and second transaction states received from the transaction monitor 60.Type: GrantFiled: July 18, 2013Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Publication number: 20160328340Abstract: A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Publication number: 20160328000Abstract: A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Patent number: 9448953Abstract: The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system 100 includes a bus monitor 50 connected to the system bus 10 to monitor the frequency of access requests from the CPU 20 to the memory subsystem 30, and a latency changing means 60 for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor.Type: GrantFiled: July 18, 2013Date of Patent: September 20, 2016Assignee: International Business Machines CorporationInventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Patent number: 9376577Abstract: The present invention relates to a coating composition containing a colored aluminum pigment and a titanium oxide pigment, wherein in the case where a coating film formed from the coating composition is illuminated at 45 degrees with respect to the surface of the coating film, a ratio of lightness L* of light observed at 45 degrees with respect to specularly reflected light, relative to lightness L* of light observed at 110 degrees with respect to specularly reflected light is within a range of 1.00 to 1.50. The invention further relates to a method for forming a coating film, including steps of applying the above-described coating composition to a substrate; and further applying a clear coating composition thereto.Type: GrantFiled: January 13, 2011Date of Patent: June 28, 2016Assignee: KANSAI PAINT CO., LTD.Inventors: Hiroshi Shimizu, Norio Fujita
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Publication number: 20150347292Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.Type: ApplicationFiled: May 28, 2015Publication date: December 3, 2015Inventor: NORIO FUJITA
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Publication number: 20140025855Abstract: The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system 100 includes a bus monitor 50 connected to the system bus 10 to monitor the frequency of access requests from the CPU 20 to the memory subsystem 30, and a latency changing means 60 for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor.Type: ApplicationFiled: July 18, 2013Publication date: January 23, 2014Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Publication number: 20140025853Abstract: The present invention provides a computer system including a CPU with an L2 cache, a bus master device and a bus slave device. They are connected via a system bus to communicate with each other. The computer system 100 includes: a transaction monitor 60 for monitoring first transaction states TrC1-TrCn between a CPU 20 and an L2 cache 25, and second transaction states from TrB0 to TrBn between a system bus 10 and the L2 cache 25, between the system bus 10 and a bus master device 30 or between the system bus 10 and bus slave devices 40, 42; and a clock generator 70 able to change the frequency FreqC1-FreqS2 of the clock of the CPU 20, the system bus 10, and the bus slave devices 40, 42 according to the first transaction and second transaction states received from the transaction monitor 60.Type: ApplicationFiled: July 18, 2013Publication date: January 23, 2014Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
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Publication number: 20120295032Abstract: The present invention relates to a coating composition containing a colored aluminum pigment and a titanium oxide pigment, wherein in the case where a coating film formed from the coating composition is illuminated at 45 degrees with respect to the surface of the coating film, a ratio of lightness L* of light observed at 45 degrees with respect to specularly reflected light, relative to lightness L* of light observed at 110 degrees with respect to specularly reflected light is within a range of 1.00 to 1.50. The invention further relates to a method for forming a coating film, including steps of applying the above-described coating composition to a substrate; and further applying a clear coating composition thereto.Type: ApplicationFiled: January 13, 2011Publication date: November 22, 2012Inventors: Hiroshi Shimizu, Norio Fujita
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Patent number: 7843742Abstract: The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a writeType: GrantFiled: July 26, 2006Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Toshio Sunaga, Norio Fujita
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Publication number: 20100061156Abstract: The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a writeType: ApplicationFiled: July 26, 2006Publication date: March 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshio Sunaga, Norio Fujita
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Publication number: 20080320236Abstract: A system includes processor units, caches, memory shared by the processor units, a system bus interface, and a cache snoop interfaces. Each processor unit has one of the caches. The system bus interface communicatively connects the processor units to the memory via at least the caches, and is a non-cache snoop system bus interface. The cache snoop interface communicatively connects the caches, and is independent of the system bus interface. Upon a given processor unit writing a new value to an address within the memory such that the new value and the address are cached within the cache of the given processor unit a write invalidation event is sent over the cache snoop interface to the caches of the processor units other than the given processor unit. This event invalidates the address as stored within any of the caches other than the cache of the given processor unit.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Inventors: Makoto Ueda, Kenichi Tsuchiya, Takeo Nakada, Norio Fujita
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Patent number: 7298789Abstract: Wireless data communication method and apparatus using two electromagnetic signals having different polarizations. Codes related to relative values of the amplitudes of the two signals are generated in correspondence with data to be transmitted. The signals are modulated according to the codes using phase shift keying and amplitude shift keying. The amplitude shift keying modulates the two electromagnetic signals by changing the difference between their two amplitudes in accordance with data encodings. The two signals are transmitted to receiver, which decodes the phases and relative amplitudes to obtain the codes, and reproduces the data from the obtained codes.Type: GrantFiled: February 6, 2004Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventors: Hiroaki Kubo, Norio Fujita