Patents by Inventor Norio Hatakeyama

Norio Hatakeyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including filling material provided in space defined by three semiconductor chips
    Patent number: 9443823
    Abstract: A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each other, a third semiconductor chip mounted on the first and second semiconductor chips, first and second adhesive layers that are provided between the first and second semiconductor chips and the wiring substrate so as to bond the first and second semiconductor chips to the wiring substrate, and a third adhesive layer that is provided between the third semiconductor chip and the first and second semiconductor chips so as to bond the third semiconductor chip to the first and second semiconductor chips, with its thickness being made thicker than that of the first and second adhesive layers, a sealing layer covering the wiring substrate, and a filling layer that is provided between the first and second semiconductor chips and is different from the sealing layer.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Norio Hatakeyama
  • SEMICONDUCTOR DEVICE INCLUDING FILLING MATERIAL PROVIDED IN SPACE DEFINED BY THREE SEMICONDUCTOR CHIPS
    Publication number: 20150333038
    Abstract: A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each other, a third semiconductor chip mounted on the first and second semiconductor chips, first and second adhesive layers that are provided between the first and second semiconductor chips and the wiring substrate so as to bond the first and second semiconductor chips to the wiring substrate, and a third adhesive layer that is provided between the third semiconductor chip and the first and second semiconductor chips so as to bond the third semiconductor chip to the first and second semiconductor chips, with its thickness being made thicker than that of the first and second adhesive layers, a sealing layer covering the wiring substrate, and a filling layer that is provided between the first and second semiconductor chips and is different from the sealing layer.
    Type: Application
    Filed: May 7, 2015
    Publication date: November 19, 2015
    Inventor: Norio Hatakeyama