Abstract: Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.

Abstract: A semiconductor memory device capable of smoothing the number of cycles of programming/erasing between blocks is provided. The semiconductor memory device includes: a memory cell array; an address translation table defining a relationship between logical address information and physical address information; an invalid block table managing the physical address information for identifying to-be-erased blocks of the blocks; a free block table managing the physical address information used for identifying erased usable blocks; an erasing element for erasing the blocks; a controller. When an erasing command and first logical address information are received from environment, the controller erases the block of the physical address information selected from the invalid block table, and rewrites the address translation table in a manner that the physical address information selected from the free block table corresponds to the first logical address information received from the external environment.

Abstract: A semiconductor storage device exhibiting improved programming reliability is provided. In the disclosure, flash memory includes a storage controller and a NAND type storage device. The storage controller includes a voltage detecting part, SRAM, RRAM, and a writer/selector. The voltage detecting part detects whether a power supply voltage drops to a fixed voltage. The SRAM stores a conversion table for converting a logical address into a physical address. The RRAM stores the logical address of a block and a page currently being programmed and conversion information for converting the logical address into another physical address when the fixed voltage is detected by the voltage detecting part during a programming process. The writer/selector converts the inputted logical address into the physical address according to the conversion table or the conversion information of the RRAM and programs data on the page of the block selected according to the converted physical address.

Abstract: Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.

Abstract: A semiconductor storage apparatus of high convenience, which improves utilization efficiency of a memory region, is provided. A flash memory provided in the disclosure includes a memory controller and an NAND memory device. The memory controller includes an SRAM, an RRAM, and a write/selector. The SRAM stores a conversion table that converts a logical address into a physical address. The RRAM temporarily stores a small amount of data which should be programmed. The write/selector selectively writes the to-be-programmed data into the RRAM or an NAND memory unit of the NAND memory device.

Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.

Abstract: Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.

Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.

Abstract: A semiconductor memory device capable of smoothing the number of cycles of programming/erasing between blocks is provided. The semiconductor memory device includes: a memory cell array; an address translation table defining a relationship between logical address information and physical address information; an invalid block table managing the physical address information for identifying to-be-erased blocks of the blocks; a free block table managing the physical address information used for identifying erased usable blocks; an erasing element for erasing the blocks; a controller. When an erasing command and first logical address information are received from environment, the controller erases the block of the physical address information selected from the invalid block table, and rewrites the address translation table in a manner that the physical address information selected from the free block table corresponds to the first logical address information received from the external environment.

Abstract: A semiconductor storage apparatus of high convenience, which improves utilization efficiency of a memory region, is provided. A flash memory provided in the disclosure includes a memory controller and an NAND memory device. The memory controller includes an SRAM, an RRAM, and a write/selector. The SRAM stores a conversion table that converts a logical address into a physical address. The RRAM temporarily stores a small amount of data which should be programmed. The write/selector selectively writes the to-be-programmed data into the RRAM or an NAND memory unit of the NAND memory device.

Abstract: A semiconductor storage device exhibiting improved programming reliability is provided. In the disclosure, flash memory includes a storage controller and a NAND type storage device. The storage controller includes a voltage detecting part, SRAM, RRAM, and a writer/selector. The voltage detecting part detects whether a power supply voltage drops to a fixed voltage. The SRAM stores a conversion table for converting a logical address into a physical address. The RRAM stores the logical address of a block and a page currently being programmed and conversion information for converting the logical address into another physical address when the fixed voltage is detected by the voltage detecting part during a programming process. The writer/selector converts the inputted logical address into the physical address according to the conversion table or the conversion information of the RRAM and programs data on the page of the block selected according to the converted physical address.

Abstract: Provided is a variable resistance random-access memory for suppressing degradation of performance by recovering a memory cell that fails. A variable resistance random-access memory of the disclosure includes a memory array, a row selection circuit, a column selection circuit, a controller, an error checking and correcting (ECC) circuit, an error bit flag register, and an error bit address register. The memory array includes a plurality of memory cells. The column selection circuit includes a sense amplifier and a write driver/read bias circuit. The error bit flag register stores bits for indicating presence/absence of an error bit in a write operation. The error bit address register stores an address of the error bit. The controller recovers the error bit when a predetermined event occurs.

Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.

Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.

Abstract: A regulator circuit includes: a detection circuit, for outputting a feedback voltage in accordance with an output voltage; a reference voltage input section; a feedback voltage input section; an operational amplification circuit, for comparing a reference voltage and the feedback voltage and outputting a voltage as a comparison result; an output circuit, for supplying an output voltage in accordance with the output of the operational amplification circuit; a connection/disconnection circuit, for connecting or disconnecting the output terminal of the detection circuit and the feedback voltage input section; and a voltage setup circuit, for setting for the feedback voltage input section a predetermined voltage. In the standby state, the connection/disconnection circuit disconnects the output terminal of the detection circuit from the feedback voltage input section, and the voltage setup circuit sets a predetermined voltage for the feedback input section.

Abstract: A memory cell array with a group of memory cells capable of retaining two-bit information. Each memory cell has a pair of transistors having charge storage regions, mutually connected gates, and mutually connected sources. Word lines are provided to the gates of the transistors. Bit lines are provided to the sources and drains of the transistors. A pair of the bit lines respectively connected to the drains of a pair of transistors included in a memory cell are connected to a comparison input terminal of the differential detector. An information retained in the memory cell is read based on a comparison result of current amounts inputted to the differential detector via the pair of bit lines obtained by the differential detector in a state where memory cell currents are simultaneously and independently supplied to the pair of transistors.

Abstract: A memory cell array comprises a group of memory cells capable of retaining two-bit information. The memory cell has a pair of transistors having charge storage regions and arranged along a row direction of the memory cell array. Word lines are provided between the memory cells adjacent to each other along a column direction of the memory cell array and extend along the row direction. Bit lines are provided between the transistors adjacent to each other along the row direction and extend along the column direction. Gates of the pair of transistors constituting the respective memory cells are connected to each other and further connected to the word line corresponding to the relevant memory cell. Sources of the pair of transistors are connected to each other and further connected to the bit lines provided between the relevant pair of transistors.

Abstract: A regulator circuit includes: a detection circuit, for outputting a feedback voltage in accordance with an output voltage; a reference voltage input section; a feedback voltage input section; an operational amplification circuit, for comparing a reference voltage and the feedback voltage and outputting a voltage as a comparison result; an output circuit, for supplying an output voltage in accordance with the output of the operational amplification circuit; a connection/disconnection circuit, for connecting or disconnecting the output terminal of the detection circuit and the feedback voltage input section; and a voltage setup circuit, for setting for the feedback voltage input section a predetermined voltage. In the standby state, the connection/disconnection circuit disconnects the output terminal of the detection circuit from the feedback voltage input section, and the voltage setup circuit sets a predetermined voltage for the feedback input section.

Abstract: A level shift circuit realizes a high-speed and power-saved operation particularly when the input voltage is at a low level. The level shift circuit includes a first gate voltage control circuit controlled by an inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from “H” to “L”, the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and the voltage of the second output terminal goes down.

Abstract: A level shift circuit which realizes a high-speed and power-saved operation particularly when the input voltage is at a low level is provided. The level shift circuit of the present invention comprises a first gate voltage control circuit controlled by a inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from “H” to “L”, the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and then the voltage of the second output terminal goes down.