Patents by Inventor Norio Kido
Norio Kido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11029740Abstract: There is to provide a power conversion device capable of estimating a junction temperature of a power transistor at a high accuracy. The control device includes a temperature estimation unit and controls the on and off of the power transistor through a driver. The voltage detection circuit detects the inter-terminal voltage of a source and drain terminals during the on-period of the power transistor. The temperature estimation unit previously holds the correlation information between the inter-terminal voltage and inter-terminal current of the source and drain terminals and the junction temperature, and estimates the junction temperature, based on the inter-terminal voltage detected by the voltage detection circuit, the known inter-terminal current, and the correlation information.Type: GrantFiled: November 13, 2018Date of Patent: June 8, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shunichi Kaeriyama, Norio Kido
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Patent number: 10546839Abstract: An electronic apparatus includes a wiring board including a main surface on which a first wiring and a second wiring are formed, a first semiconductor device mounted on the main surface of the wiring board, and a second semiconductor device mounted on the main surface of the wiring board. Each of the first semiconductor device and the second semiconductor device includes a first semiconductor chip including an insulated gate bipolar transistor, a second semiconductor chip including a diode, a first lead electrically connected to an emitter electrode pad formed on a first front surface of the first semiconductor chip, a second lead electrically connected to an anode electrode pad formed on a second front surface of the second semiconductor chip, and a first terminal electrically connected to a collector electrode formed on a first back surface of the first semiconductor chip.Type: GrantFiled: September 28, 2018Date of Patent: January 28, 2020Assignee: RENESAS ELECTRONIC CORPORATIONInventors: Akira Muto, Norio Kido
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Publication number: 20190204889Abstract: There is to provide a power conversion device capable of estimating a junction temperature of a power transistor at a high accuracy. The control device includes a temperature estimation unit and controls the on and off of the power transistor through a driver. The voltage detection circuit detects the inter-terminal voltage of a source and drain terminals during the on-period of the power transistor. The temperature estimation unit previously holds the correlation information between the inter-terminal voltage and inter-terminal current of the source and drain terminals and the junction temperature, and estimates the junction temperature, based on the inter-terminal voltage detected by the voltage detection circuit, the known inter-terminal current, and the correlation information.Type: ApplicationFiled: November 13, 2018Publication date: July 4, 2019Inventors: Shunichi KAERIYAMA, Norio KIDO
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Publication number: 20190088629Abstract: An electronic apparatus includes a wiring board including a main surface on which a first wiring and a second wiring are formed, a first semiconductor device mounted on the main surface of the wiring board, and a second semiconductor device mounted on the main surface of the wiring board. Each of the first semiconductor device and the second semiconductor device includes a first semiconductor chip including an insulated gate bipolar transistor, a second semiconductor chip including a diode, a first lead electrically connected to an emitter electrode pad formed on a first front surface of the first semiconductor chip, a second lead electrically connected to an anode electrode pad formed on a second front surface of the second semiconductor chip, and a first terminal electrically connected to a collector electrode formed on a first back surface of the first semiconductor chip.Type: ApplicationFiled: September 28, 2018Publication date: March 21, 2019Inventors: Akira Muto, Norio Kido
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Patent number: 10217727Abstract: For example, a semiconductor device capable of achieving a high performance applicable to an SR motor is provided. The semiconductor device includes a chip mounting portion TAB1 on which a semiconductor chip CHP1 having an IGBT is mounted, and a chip mounting portion TAB2 on which a semiconductor chip CHP2 having a diode is formed. The semiconductor device also includes a lead LD1A electrically connected to an emitter electrode pad EP of the semiconductor chip CHP1 via a clip CLP1, and a lead LD1B electrically connected to an anode electrode pad ADP of the semiconductor chip CHP2 via a clip CLP2. At this time, the chip mounting portion TAB1 is separated electrically from the chip mounting portion TAB2, and the clip CLP1 is separated electrically from the clip CLP2.Type: GrantFiled: August 25, 2014Date of Patent: February 26, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akira Muto, Norio Kido
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Publication number: 20170229428Abstract: For example, a semiconductor device capable of achieving a high performance applicable to an SR motor is provided. The semiconductor device includes a chip mounting portion TAB1 on which a semiconductor chip CHP1 having an IGBT is mounted, and a chip mounting portion TAB2 on which a semiconductor chip CHP2 having a diode is formed. The semiconductor device also includes a lead LD1A electrically connected to an emitter electrode pad EP of the semiconductor chip CHP1 via a clip CLP1, and a lead LD1B electrically connected to an anode electrode pad ADP of the semiconductor chip CHP2 via a clip CLP2. At this time, the chip mounting portion TAB1 is separated electrically from the chip mounting portion TAB2, and the clip CLP1 is separated electrically from the clip CLP2.Type: ApplicationFiled: August 25, 2014Publication date: August 10, 2017Inventors: Akira MUTO, Norio KIDO
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Patent number: 9129979Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: GrantFiled: June 26, 2012Date of Patent: September 8, 2015Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Patent number: 8466549Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. The third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: GrantFiled: September 23, 2011Date of Patent: June 18, 2013Assignee: Renesas Electronics CorporationInventors: Kentaro Ochi, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Publication number: 20120261825Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Inventors: Nobuya KOIKE, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Patent number: 8232629Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: GrantFiled: August 20, 2007Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Publication number: 20120012978Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kentaro OCHI, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Patent number: 8035222Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: GrantFiled: December 15, 2010Date of Patent: October 11, 2011Assignee: Renesas Electronics CorporationInventors: Kentaro Ochi, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Patent number: 7969000Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.Type: GrantFiled: February 16, 2010Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Norio Kido, Tatsuhiro Seki, Katsuo Ishizaka, Ichio Shimizu
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Publication number: 20110084359Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: ApplicationFiled: December 15, 2010Publication date: April 14, 2011Inventors: Kentaro OCHI, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Patent number: 7872348Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: GrantFiled: June 9, 2010Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventors: Kentaro Ochi, Akira Mishima, Takuro Kanazawa, Tetsuo Iijima, Katsuo Ishizaka, Norio Kido
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Publication number: 20100315786Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.Type: ApplicationFiled: June 9, 2010Publication date: December 16, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kentaro OCHI, Akira MISHIMA, Takuro KANAZAWA, Tetsuo IIJIMA, Katsuo ISHIZAKA, Norio KIDO
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Publication number: 20100140718Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.Type: ApplicationFiled: February 16, 2010Publication date: June 10, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yukihiro Sato, Norio Kido, Tatsuhiro Seki, Katsuo Ishizaka, Ichio Shimizu
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Patent number: 7692285Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.Type: GrantFiled: June 29, 2006Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Yukihiro Sato, Norio Kido, Tatsuhiro Seki, Katsuo Ishizaka, Ichio Shimizu
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Publication number: 20080054422Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: ApplicationFiled: August 20, 2007Publication date: March 6, 2008Inventors: Nobuya KOIKE, Atsushi FUJIKI, Norio KIDO, Yukihiro SATO, Hiroyuki NAKAMURA
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Publication number: 20070001273Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP(semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the PMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.Type: ApplicationFiled: June 29, 2006Publication date: January 4, 2007Inventors: Yukihiro Sato, Norio Kido, Tatsuhiro Seki, Katsuo Ishizaka, Ichio Shimizu