Patents by Inventor Norio Koizumi

Norio Koizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6317344
    Abstract: A semiconductor device that is capable of preventing erroneous operation such as momentary lighting, comprising a booster circuit to which first and second power supply potentials VDD and VSS are supplied from an external power source, for boosting the absolute value of the potential difference therebetween and charging the boosted potential to a capacitor. This booster circuit has a plurality of transistors and a plurality of capacitors, and the boosted potential is charged to one of the plurality of capacitors in accordance with how the plurality of transistors are turned on or off. The gates of a plurality of transistors are connected to output lines of first and second NAND circuits, to which the output of a comparator is input through a buffer.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: November 13, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Norio Koizumi, Masahiko Tsuchiya
  • Patent number: 6300797
    Abstract: A semiconductor device capable of preventing malfunctions of instantaneous lighting, and comprises a drive circuit, a drive control circuit, and a power supply circuit. The power supply circuit has a boosting circuit which is provided with a first power supply potential VDD being a ground potential from an external power supply and a second power supply potential VSS, being a potential other than the ground potential, and raises the absolute value of the second power supply potential VSS and charges to the capacitor; and a bias generating circuit generating a potential to be supplied to the drive circuit and drive control circuit based on the output potential of the boosting circuit.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: October 9, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Norio Koizumi
  • Patent number: 6181584
    Abstract: A semiconductor device that is capable of preventing erroneous operation such as momentary lighting, having a booster circuit to which first and second power supply potentials VDD and VSS are supplied from an external power source, for boosting the absolute value of the potential difference therebetween and charging the boosted potential to a capacitor. This booster circuit has a plurality of transistors and a plurality of capacitors, and the boosted potential is charged to one of the plurality of capacitors in accordance with how the plurality of transistors are turned on or off. The gates of a plurality of transistors are connected to output lines of first and second NAND circuits, to which the output of a comparator is input through a buffer.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: January 30, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Norio Koizumi, Masahiko Tsuchiya
  • Patent number: 6075420
    Abstract: An oscillation device includes a buffer device, a feedback device for feeding back an output of the buffer device to an input thereof and a charging device and a discharging device connected to the input of the buffer device. The charging device includes a first switching device that is turned on and off based on the output of the buffer device and a first current control device that controls the current flowing into the input of the buffer device through the first switching device. The discharging device includes a second switching device that is turned on or off based on the output of the buffer device and a second current control device that controls the current flowing out of the input of the buffer device through the second switching device. The first and second switching devices include first and second transistors and the first and second current sources that include third and fourth transistors.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: June 13, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Yoichi Imamura, Shigeki Aoki, Norio Koizumi
  • Patent number: 5896114
    Abstract: The present invention provides a matrix type display device which simplifies the process in a display signal generating circuit while relieving the load on an external CPU, and which arranges freely character and icon display areas while preventing the quality of display from being degraded by the shadow phenomenon and others. A display code memory stores character display codes and icon display codes for one image at a desired address arrangement. A pattern generating circuit transfers image patterns for the display codes to a display signal transferring circuit through a multiplexer. A decoder selecting device is responsive to a decoder select signal to select a decoder, thereby controlling voluntarily the timing of latch signal generation. Display signal input in the time division manner is latched in first and second latch circuits through the latch signal. Thereafter, the display signal is transferred to a signal electrode driving circuit through a line memory to display an image on a matrix panel.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: April 20, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Yohichi Imamura, Shigeki Aoki, Norio Koizumi
  • Patent number: 5784072
    Abstract: An oscillation device and a display data processing device adjust variables such as the duty ratio of the oscillation frequency, and control autonomously timings between components such as memories. First and second switching devices disposed within charging and discharging devices are turned on and off by an output of a MOS buffer, enabling adjustment of the frequency and duty ratio of an oscillation signal. Equivalent circuits are provided corresponding to display data RAM, CGROM, and address decoders, data is read sequentially from the display data RAM and the CGROM when an EIRAM signal is enabled, and a DLAT signal is stored in a driver circuit. The equivalent circuits enable each of EIROM, EILAT, and RS signals at points when the read data is confirmed or thereafter. When the RS signal is enabled, EIRAM and other signals are sequentially disabled and the display data RAM and other components switch to a precharge operation.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: July 21, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Yoichi Imamura, Shigeki Aoki, Norio Koizumi
  • Patent number: 5742271
    Abstract: The present invention provides a matrix type display device which simplifies the process in a display signal generating circuit while relieving the load on an external CPU, which arranges freely character and icon display areas while preventing the quality of display from being degraded by the shadow phenomenon and others. A display code memory stores character display codes and icon display codes for one image at a desired address arrangement. A pattern generating circuit transfers image patterns for the display codes to a display signal transferring circuit through a multiplexer. A decoder selecting device is responsive to a decoder select signal to select a decoder, thereby controlling voluntarily the timing of latch signal generation. Display signal input in the time division manner is latched in first and second latch circuits through the latch signal. Thereafter, the display signal is transferred to a signal electrode driving circuit through a line memory to display an image on a matrix panel.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: April 21, 1998
    Assignee: Seiko Epson Corporaiton
    Inventors: Yohichi Imamura, Shigeki Aoki, Norio Koizumi