Abstract: A PLL circuit comprises a reference signal generating unit for generating reference signals of different phases, variable frequency dividers for dividing the frequency of the output signal of a voltage-controlled oscillator (VCO) and thereby outputting feedback signals, and a phase comparator for comparing the phase of each feedback signal with that of the corresponding reference signal and thereby outputting phase comparison signals. When the output signal is synchronized with a preset frequency signal, at least one variable frequency divider of the variable frequency dividers is operated, and the operation of the other is stopped.

Abstract: A PLL circuit comprises a reference signal generating unit for generating reference signals of different phases, variable frequency dividers for dividing the frequency of the output signal of a voltage-controlled oscillator (VCO) and thereby outputting feedback signals, and a phase comparator for comparing the phase of each feedback signal with that of the corresponding reference signal and thereby outputting phase comparison signals. When the output signal is synchronized with a preset frequency signal, at least one variable frequency divider of the variable frequency dividers is operated, and the operation of the other is stopped.