Abstract: A radio terminal device realizing reduced power consumption and prompt detection of detection object by using a first sensor and a second sensor whose ON/OFF states are opposite and whose operations are synchronized. When the first sensor detects a detection object, the first output voltage level is changed. When a processor detects the change of the output voltage level as an interrupt signal, the drive voltage level of the first sensor is switched to low and the drive voltage level of the second sensor is switched to high. Moreover, when the second sensor detects a detection object, the output voltage level of the second sensor is changed. When the processor detects the change of the output voltage level as an interrupt signal, the drive voltage level of the second sensor is switched to low and the drive voltage level of the first circuit is switched to high.

Abstract: There is provided a generator generating power from vibration, capable of increasing a power generation voltage even if the vibration is small in amplitude to thereby enhance efficiency of power generation. A vibration power generator, provided with a mechanism for converting vibrational energy into electrical energy, comprises a switch for switching over whether or not power is outputted, and control of the switch is executed by periodic control thereof such that switchover occurs between respective time periods for outputting the power and respective time periods for not outputting the power at cycles not less than twice and not more than 100 times cycles of vibration. With the invention, efficiency of the generator can be enhanced, and it is possible to provide electronic equipment without power supply from outside, and capable of saving trouble of battery replacement.

Abstract: A piezoelectric power generation system which performs a highly efficient power generation using a piezoelectric element without dependency on the direction of an externally driven vibration. The piezoelectric power generation system includes a vibrator having a beam in the form of a rod, and an impact element such as a steel ball. At one end of the beam is fixed the impact element, and at the other end of the beam, the beam is fixed to the base. The outer circumference of the impact element carries the cylinder shaped piezoelectric element. When the base vibrates due to an externally driven vibration, the vibrator vibrates in synchronization with the given vibration in the radial direction of the base to cause the impact element of the base to impact with the inner surface of the cylindrical piezoelectric element, forcing the piezoelectric element to deform and thereby generate electrical power.

Abstract: Unnecessary moment in a vibrator is remarkably reduced and the power generation efficiency in capacitance-type vibrational power generation is remarkably improved. A vibrator provided in a variable-capacitance type vibrator has a structure in that one ends of oscillation plates extending in a longitudinal direction thereof sandwiches a mass and the other ends thereof sandwiches a spacer, respectively, wherein the oscillation plates are arranged parallel to each other. A space portion between the oscillation plates and in which the mass and the spacer are not in contact with each other functions as a spring. By holding the mass by the two oscillation plates, the mass can be oscillated while it is in parallel to an opposing electrode. Therefore, generation of unnecessary moment in a direction other than an oscillation direction can be remarkably reduced.

Abstract: The present invention provides a high-speed processing and high precision delay calculation method of semiconductor integrated circuit devices having a plurality of cells and interconnections connecting therebetween, with less data to be obtained prior to delay calculation. The method comprises the steps of: calculating temporary delay T0 that is the delay of the cell on the basis of total load capacitance Ct of the capacitance values connected to the output of the cell; calculating the voltage Vc at the node connected to the load capacitance C connected to the output of the cell at the temporary delay T0; calculating effective load capacitance Ceff by multiplying the ratio of the voltage Vc to the voltage Vtb defining the delay with the capacitance C; calculating the cell delay Tc on the basis of the effective load capacitance Ceff.

Abstract: There is provided a delay calculation method considering a shield effect applicable to delay calculation for a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires. A method for replacing a circuit connected to the output pin of an electronic circuit cell by one effective capacitance to calculate a delay in the electronic circuit cell, comprising procedure (111) which inputs a load parameter in which a circuit connected to the output pin is expressed by an equivalent circuit including resistances and capacitances or inductances, procedure (101) which calculates voltage of capacitance node of the equivalent circuit at transition time until the voltage of the output pin reaches a definition voltage for delay, procedure (103) which calculates the effective capacitance from the voltage of the capacitance node, and procedure (104) which calculates a delay (112) in the electronic circuit cell from the effective capacitance.

Abstract: There is provided a method of displaying calculated delay which can easily grasp the state of the entire logical block and acquire the detailed information on delay violation paths. A display screen has a first window displaying a path delay list of a combination of a source and a sink of a path and a second window displaying a cell delay list of cells corresponding to the route of the path. A path is selected on the first window to display the detail of the corresponding path on the second window. It is easily possible to grasp the state of the entire logical block and acquire the detailed information on delay violation paths. The design period of a semiconductor integrated circuit can be reduced largely.

Abstract: There is provided a delay calculation method considering a shield effect applicable to delay calculation for a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires.

Abstract: A method of fabricating semiconductor integrated circuits with an improved yield rate is realized, which requires no special circuits for selecting normal circuit blocks. Removable temporary wires are connected to circuit blocks, which are thus tested. After removing the temporary wires, a plurality of normally-operating circuit blocks are interconnected by new main wires. The need of a special selecting circuit for replacing defective circuit blocks with normal circuit blocks is eliminated without increasing the delay time due to redundancy. The freedom of the main wiring formed after removal of the temporary wires is so high that the functional freedom of the system constructed is improved.

Abstract: A carry look ahead circuit includes a first circuit for generating a logical sum of inputs, a second circuit for generating a logical product of the inputs, and a selection circuit for selecting either one of an output of the first circuit and an output of the second circuit in accordance with a carry signal from a lower figure to produce the selected output as a carry signal. Consequently, the number of circuit elements can be reduced greatly to configure the high speed and low power consumption carry look ahead circuit.