Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in aeries together is disclosed. A select gate translator is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate translator is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device is provided having a plurality of electrically rewritable nonvolatile memory cells connected in series together. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with a different bias voltage as that for the other memory cells.

Abstract: A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.

Abstract: A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together is disclosed. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.