Patents by Inventor Norio Sadachika

Norio Sadachika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit simulation of MOSFETs
    Patent number: 8731893
    Abstract: An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 20, 2014
    Assignee: Hiroshima University, a National University Corporation of Japan
    Inventors: Mitiko Miura-Mattausch, Norio Sadachika, Shunta Kusu, Takaki Yoshida
  • SIMULATION METHOD AND SIMULATION APPARATUS
    Publication number: 20110184708
    Abstract: An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by, iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.
    Type: Application
    Filed: April 5, 2011
    Publication date: July 28, 2011
    Inventors: Mitiko MIURA-MATTAUSCH, Norio Sadachika, Shunta Kusu, Takaki Yoshida
  • Simulation method and simulation apparatus for LDMOSFET
    Patent number: 7983889
    Abstract: The drift region for increasing the breakdown voltage in an LDMOSFET is regarded as a resistive element. The potential distribution of the overall device is calculated by obtaining a potential distribution considering the resistance by iterative calculation. A capacitance generated in the drift region is analytically calculated assuming a linear potential distribution. A capacitance generated in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: July 19, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Mitiko Miura, Masahiro Yokomichi, Takahiro Kajiwara, Norio Sadachika, Masataka Miyake, Takahiro Iizuka, Masahiko Taguchi, Tatsuya Ohguro
  • SIMULATION METHOD AND SIMULATION APPARATUS FOR LDMOSFET
    Publication number: 20090070084
    Abstract: The drift region for increasing the breakdown voltage in an LDMOSFET is regarded as a resistive element. The potential distribution of the overall device is calculated by obtaining a potential distribution considering the resistance by iterative calculation. A capacitance generated in the drift region is analytically calculated assuming a linear potential distribution. A capacitance generated in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.
    Type: Application
    Filed: May 30, 2008
    Publication date: March 12, 2009
    Inventors: Mitiko Miura, Masahiro Yokomichi, Takahiro Kajiwara, Norio Sadachika, Masataka Miyake, Takahiro Iizuka, Masahiko Taguchi, Tatsuya Ohguro