Patents by Inventor Norio Sengoku

Norio Sengoku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6272020
    Abstract: A semiconductor device-mounting substrate is provided with a semiconductor device, a capacitor device, and a wiring substrate. The wiring substrate has a space in which the capacitor device should be located, and the capacitor device is locate in the space. Terminals of a driving power supply wiring for the semiconductor device are provided on a surface of the space, and the terminals are connected with the capacitor device.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: August 7, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiromi Tosaki, Takaji Takenaka, Kazutoshi Takahashi, Norio Sengoku, Toshitada Netsu
  • Patent number: 6118671
    Abstract: Ceramic circuit substrate which is sintered at 900 to 1,050.degree. C. and have low relative dielectric constant, thermal expansion coefficient comparable to that of silicon, and high bending strength, and a method of manufacturing are provided by using a glass with a softening point of 850 to 1,100.degree. C., that is, a glass having a composition included in an area in FIG. 1 (triangular composition diagram of SiO.sub.2 --B.sub.2 O.sub.3 --R.sub.2 O, a composition is represented by the position of a small circle, the number in a small circle represents the composition number) defined with lines connecting points representing the first, third, tenth, eleventh, and fourth compositions respectively as raw material.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: September 12, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hirayoshi Tanei, Shoichi Iwanaga, Masahide Okamoto, Masato Nakamura, Kousaku Morita, Shousaku Ishihara, Fumikazu Tagami, Norio Sengoku, Tsuyoshi Fujita, Fumiyuki Kobayashi
  • Patent number: 5825632
    Abstract: Ceramic circuit substrate which is sintered at 900.degree. to 1,050.degree. C. and have low relative dielectric constant, thermal expansion coefficient comparable to that of silicon, and high bending strength, and a method of manufacturing are provided by using a glass with a softening point of 850.degree. to 1,100.degree. C., that is, a glass having a composition included in an area in FIG. 1 (triangular composition diagram of SiO.sub.2 --B.sub.2 O.sub.3 --R.sub.2 O, a composition is represented by the position of a small circle, the number in a small circle represents the composition number) defined with lines connecting points representing the first, third, tenth, eleventh, and fourth compositions respectively as raw material.
    Type: Grant
    Filed: August 8, 1995
    Date of Patent: October 20, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hirayoshi Tanei, Shoichi Iwanaga, Masahide Okamoto, Masato Nakamura, Kousaku Morita, Shousaku Ishihara, Fumiyuki Kobayashi, Fumikazu Tagami, Norio Sengoku, Tsuyoshi Fujita
  • Patent number: 5040992
    Abstract: A first mother board among a plurality of mother boards is mounted adjacent to a reference mother board and a second mother board among said plurality of mother boards is mounted in a position rotated 180.degree. about the horizontal centerline of the second mother board and mounted back to back to the first mother board, whereby the reference mother board and the first and second mother boards can be interconnected at a minimal distance.
    Type: Grant
    Filed: December 4, 1989
    Date of Patent: August 20, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Miyamoto, Fumiyuki Kobayashi, Shizuo Zushi, Norio Sengoku, Yoshiaki Horita
  • Patent number: 4899251
    Abstract: In a power supply network network of a printed circuit board, a through hole network for power supply electrically connected to main power supply pads connected with power supply cables is electrically and substantially independent of an internal network comprising networks of power supply layers on the like and a through hold network for load. Thereby, each of source currents supplied from the power supply cables reaches the through hole network for each load, once, via the through hold network for power supply and horizontal buses, therefore the dispersion in the drop of voltage across the main power supply pads and each of the loads is effectively decreased.
    Type: Grant
    Filed: October 28, 1988
    Date of Patent: February 6, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Imai, Norio Sengoku
  • Patent number: 4884170
    Abstract: A multilayer printed circuit board having a plurality of printed circuit boards each having opposite surfaces respectively provided with an electric source or ground layer and a signal circuit layer. The plurality of printed circuit boards is stacked through adhesive layers such that the electric source or ground layer and the signal circuit layer are alternately disposed, the characteristic impedance of each signal circuit layer is given by a thickness and material of each of the substrate and the adhesive sheet disposed between the signal circuit layer and one of two electric source or ground layers adjacent to the signal circuit layer and between the same signal circuit layer and the other electric source or ground layer.
    Type: Grant
    Filed: April 14, 1983
    Date of Patent: November 28, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Nobuaki Ohki, Norio Sengoku, Fumiyuki Kobayashi
  • Patent number: 4616292
    Abstract: In a multilayer printed circuit board including a signal layer, a power supply layer, and through-holes, the shape of each of clearances formed on a power supply layer for the purpose of attaining insulation from through-holes is nearly a quadrangle having four circular corners. Thereby, the area of the power supply layer left between adjacent clearances is increased to suppress increase in electrical resistance at that portion.
    Type: Grant
    Filed: July 22, 1985
    Date of Patent: October 7, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Norio Sengoku, Hiroshi Kozai, Fumiyuki Kobayashi
  • Patent number: 4614559
    Abstract: A method of fabricating a multilayer printed-circuit composite in which a plurality of internal layer sheets are stacked in an alternate arrangement with one another and laminated together. The relatively thin and thick internal layer sheets are stacked alternately with adhesive material sheets being interposed between the adjacent internal layer sheets. By melting the adhesive material sheets, the stacked internal layer sheets are laminated together. This structure of the multilayer printed-circuit board is effective for reducing the dimensional changes of the internal layer sheet when compared with the structure composed only of thin internal layer sheets. Thus, the multilayer printed-circuit composite can be realized in a relatively small overall thickness while reducing the dimensional changes of the individual internal layer sheets.
    Type: Grant
    Filed: December 21, 1984
    Date of Patent: September 30, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Hisato Shirasawa, Norio Sengoku, Nobuaki Ohki