Patents by Inventor Norio SHIROIWA

Norio SHIROIWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing mounting substrate on which monolithic ceramic capacitors are mounted and mounting structure
    Patent number: 9338889
    Abstract: A method of manufacturing a mounting substrate in which a pair of monolithic ceramic capacitors each of which includes a multilayer body in which a plurality of dielectric ceramic sheets and a plurality of substantially planar inner electrodes are stacked on top of one another and at least a pair of outer electrodes electrically connected to the inner electrodes and provided on a surface of the multilayer body are mounted on a circuit board includes a process of joining the outer electrodes to lands formed on the front rear surfaces of the circuit board, the lands formed on the front surface being formed at positions that are plane-symmetrical to positions of the corresponding lands formed on the rear surface while being electrically connected to the corresponding lands formed on the rear surface, such that surface directions of planes of the inner electrodes match each other.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: May 10, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo Hattori, Isamu Fujimoto, Norio Shiroiwa
  • METHOD OF MANUFACTURING MOUNTING SUBSTRATE ON WHICH MONOLITHIC CERAMIC CAPACITORS ARE MOUNTED AND MOUNTING STRUCTURE
    Publication number: 20140110161
    Abstract: A method of manufacturing a mounting substrate in which a pair of monolithic ceramic capacitors each of which includes a multilayer body in which a plurality of dielectric ceramic sheets and a plurality of substantially planar inner electrodes are stacked on top of one another and at least a pair of outer electrodes electrically connected to the inner electrodes and provided on a surface of the multilayer body are mounted on a circuit board includes a process of joining the outer electrodes to lands formed on the front rear surfaces of the circuit board, the lands formed on the front surface being formed at positions that are plane-symmetrical to positions of the corresponding lands formed on the rear surface while being electrically connected to the corresponding lands formed on the rear surface, such that surface directions of planes of the inner electrodes match each other.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 24, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kazuo HATTORI, Isamu FUJIMOTO, Norio SHIROIWA