Patents by Inventor Norio Yasuhara

Norio Yasuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11798997
    Abstract: A semiconductor device includes: cell and termination regions; a first electrode; a semiconductor part on the first electrode; an insulating film on the semiconductor part in the termination region; mutually-separated second electrodes on the insulating film arranged in a direction from a center toward an outer perimeter of the semiconductor part when viewed from above; a first floating electrode in the insulating film overlapping a gap between an adjacent pair of the second electrodes when viewed from above, and facing one of the pair via the insulating film; and a second floating electrode in the insulating film and separated from and overlapping the first floating electrode in the gap when viewed from above, and facing the other of the pair of second electrodes via the insulating film, wherein the overlapping portion of the second floating electrode is positioned below a portion of the first floating electrode overlapping the gap.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 24, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kenichi Matsushita, Norio Yasuhara
  • Publication number: 20230307509
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part, a structure body, and an insulating part. The semiconductor part includes first to fifth semiconductor regions. The structure body includes a gate part and a dummy part. The gate part includes at least one gate electrode. The dummy part includes at least two dummy electrodes. The gate part and the dummy part are alternately arranged. The insulating part is located between the gate electrode and the semiconductor part. The gate part is located in the fourth semiconductor region. A first potential is applied to the second electrode. A second potential that is greater than the first potential is applied to the gate electrode. A third potential that is greater than the first potential is applied to the dummy electrode located at a position next to the gate part.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 28, 2023
    Inventors: Kazuki Minamikawa, Daiki Yoshikawa, Norio Yasuhara, Kazutoshi Nakamura
  • Publication number: 20220302288
    Abstract: This semiconductor device includes: a semiconductor layer having a first face and a second face, the semiconductor layer including a first trench and a second trench in a first face side; a first gate electrode in the first trench; a first conductive layer in the first trench and between the first gate electrode and the second face, the first conductive layer being electrically separated from the first gate electrode; a second gate electrode in the second trench; a second conductive layer in the second trench and between the second gate electrode and the second face; a first electrode on a the first face side; a second electrode on a side of the second face; a first gate electrode pad being electrically connected to the first gate electrode; and a second gate electrode pad being electrically connected to the second gate electrode.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 22, 2022
    Inventors: Norio YASUHARA, Yoko IWAKAJI, Yusuke KAWAGUCHI, Daiki YOSHIKAWA, Kenichi MATSUSHITA, Shoko HANAGATA, Tomoko MATSUDAI, Hiroko ITOKAZU, Keiko KAWAMURA
  • Publication number: 20220302265
    Abstract: A semiconductor device includes: cell and termination regions; a first electrode; a semiconductor part on the first electrode; an insulating film on the semiconductor part in the termination region; mutually-separated second electrodes on the insulating film arranged in a direction from a center toward an outer perimeter of the semiconductor part when viewed from above; a first floating electrode in the insulating film overlapping a gap between an adjacent pair of the second electrodes when viewed from above, and facing one of the pair via the insulating film; and a second floating electrode in the insulating film and separated from and overlapping the first floating electrode in the gap when viewed from above, and facing the other of the pair of second electrodes via the insulating film, wherein the overlapping portion of the second floating electrode is positioned below a portion of the first floating electrode overlapping the gap.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 22, 2022
    Inventors: Kenichi MATSUSHITA, Norio YASUHARA
  • Patent number: 10438946
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Patent number: 10439038
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 8, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Patent number: 10418470
    Abstract: A semiconductor device according to an embodiment includes a first diode portion including a first trench extending in a first direction, and a first trench electrode; a second diode portion adjacent to the first diode portion in the first direction and includes a second trench extending in the first direction, and a second trench electrode and of which the width in the first direction is greater than the width of the first diode portion in a second direction perpendicular to the first direction; and a first IGBT portion adjacent to the first diode portion in the second direction and is adjacent to the second diode portion in the first direction and includes a third trench extending in the first direction, and a first gate electrode.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 17, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
  • Publication number: 20190081162
    Abstract: A semiconductor device according to an embodiment includes a first diode portion including a first trench extending in a first direction, and a first trench electrode; a second diode portion adjacent to the first diode portion in the first direction and includes a second trench extending in the first direction, and a second trench electrode and of which the width in the first direction is greater than the width of the first diode portion in a second direction perpendicular to the first direction; and a first IGBT portion adjacent to the first diode portion in the second direction and is adjacent to the second diode portion in the first direction and includes a third trench extending in the first direction, and a first gate electrode.
    Type: Application
    Filed: March 6, 2018
    Publication date: March 14, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei GEJO, Kazutoshi NAKAMURA, Norio YASUHARA, Tomohiro TAMAKI
  • Patent number: 10141455
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Publication number: 20180226487
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Application
    Filed: March 9, 2018
    Publication date: August 9, 2018
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Publication number: 20180226397
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Application
    Filed: August 30, 2017
    Publication date: August 9, 2018
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Patent number: 9941127
    Abstract: A semiconductor includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a gate electrode. The gate electrode has a first portion arranged with the second semiconductor region in a direction perpendicular to a first direction extending from the first electrode to the first semiconductor region, and has a second portion on the first portion. The semiconductor also includes a gate insulating layer between the gate electrode and each of the three semiconductor regions. The gate insulating layer extends to the upper surface of the third semiconductor region to form an extending portion. The second portion of the gate electrode protrudes in an upward direction from the upper surface of the extending portion of the gate insulating layer, and a lower part of the second portion of the gate electrode is embedded in the first portion of the gate electrode.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: April 10, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Bungo Tanaka, Norio Yasuhara
  • Publication number: 20170271451
    Abstract: A semiconductor device includes a first-conductivity type first semiconductor region, a gate electrode extending inwardly of the first semiconductor region, a gate insulation layer interposed between the gate electrode and the first semiconductor region, a second-conductivity type second semiconductor region on the first semiconductor region, a first-conductivity type third semiconductor region on selected portions of second semiconductor region, a second-conductivity type fourth semiconductor region on the first semiconductor region and spaced from the second semiconductor region, a first-conductivity type fifth semiconductor region on the fourth semiconductor region, a first insulation layer on the third and fifth semiconductor regions and extending over the gate electrode, a first electrode on the first insulation layer, and a first insulation portion extending between the second and fourth semiconductor regions.
    Type: Application
    Filed: August 30, 2016
    Publication date: September 21, 2017
    Inventors: Kenichi MATSUSHITA, Norio YASUHARA, Bungo TANAKA
  • Patent number: 9761582
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 12, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
  • Publication number: 20170186884
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Patent number: 9634128
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: April 25, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Publication number: 20170110449
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.
    Type: Application
    Filed: September 2, 2016
    Publication date: April 20, 2017
    Inventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
  • Publication number: 20170047444
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a gate electrode including: a first portion including polycrystalline silicon and arranged. with the second semiconductor region in a second.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 16, 2017
    Inventors: Bungo Tanaka, Norio Yasuhara
  • Patent number: 9496352
    Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region on the first semiconductor region; a third semiconductor region on the second semiconductor region; an fourth insulating film on the second semiconductor region and the third semiconductor region; a first electrode under the first semiconductor region; a second electrode on the fourth insulating film; a plurality of first contact regions extending in a first direction from the first electrode toward the second electrode in the fourth insulating film, and the plurality of first contact regions electrically connecting the third semiconductor region to the second electrode; a plurality of second contact regions extending in the first direction in the fourth insulating film, and one of the plurality of second contact regions between adjacent ones of the first contact regions; and a third electrode in the second semiconductor region via a first insulating film.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: November 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Norio Yasuhara, Tsuneo Ogura
  • Publication number: 20160276444
    Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region on the first semiconductor region; a third semiconductor region on the second semiconductor region; an fourth insulating film on the second semiconductor region and the third semiconductor region; a first electrode under the first semiconductor region; a second electrode on the fourth insulating film; a plurality of first contact regions extending in a first direction from the first electrode toward the second electrode in the fourth insulating film, and the plurality of first contact regions electrically connecting the third semiconductor region to the second electrode; a plurality of second contact regions extending in the first direction in the fourth insulating film, and one of the plurality of second contact regions between adjacent ones of the first contact regions; and a third electrode in the second semiconductor region via a first insulating film.
    Type: Application
    Filed: September 2, 2015
    Publication date: September 22, 2016
    Inventors: Tomoko Matsudai, Norio Yasuhara, Tsuneo Ogura