Patents by Inventor Norio Yoshimura

Norio Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10044953
    Abstract: A solid-state imaging device capable of reducing an area of a chip, capable of realizing both reduction of voltage and prevention of inversion video noise and consequently capable of realizing a higher image quality having a pixel portion and a clipping circuit capable of clipping a pixel readout voltage in accordance with a clipping voltage, wherein the pixel includes a photo-electric conversion element PD, a transfer element capable of transferring a charge accumulated in the photo-electric conversion element in a transfer period, a floating diffusion FD to which the charge accumulated in the photo-electric conversion element is transferred through a transfer element, a source-follower element which converts the charge in the floating diffusion to a voltage signal in accordance with a charge quantity, and a reset element which resets the floating diffusion to a predetermined potential in a resetting period, and the clipping circuit is arranged in an ineffective region of the pixel portion, a driving method
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 7, 2018
    Assignee: Brillnics Japan Inc.
    Inventors: Shunsuke Okura, Shinji Ohsawa, Norio Yoshimura
  • Publication number: 20180115726
    Abstract: In a solid-state imaging device, a first multiplexer array 70 is configured so that a plurality of column outputs CLM (0 to 10 . . . ) of the pixel portion 20 are formed into a plurality of groups GRP1a-1d, GRP2a-2d . . . and includes a plurality of shuffle encoders 71-0 to 71-7 . . . capable of shuffling the plurality of column outputs CLM0 to 10 . . . belonging to the groups. Further, it is configured so that, between the adjoining shuffle encoders 71, at least one column output, e.g.
    Type: Application
    Filed: April 13, 2016
    Publication date: April 26, 2018
    Applicant: Brillnics Inc.
    Inventor: Norio Yoshimura
  • Publication number: 20160373673
    Abstract: A solid-state imaging device capable of reducing an area of a chip, capable of realizing both reduction of voltage and prevention of inversion video noise and consequently capable of realizing a higher image quality having a pixel portion and a clipping circuit capable of clipping a pixel readout voltage in accordance with a clipping voltage, wherein the pixel includes a photo-electric conversion element PD, a transfer element capable of transferring a charge accumulated in the photo-electric conversion element in a transfer period, a floating diffusion FD to which the charge accumulated in the photo-electric conversion element is transferred through a transfer element, a source-follower element which converts the charge in the floating diffusion to a voltage signal in accordance with a charge quantity, and a reset element which resets the floating diffusion to a predetermined potential in a resetting period, and the clipping circuit is arranged in an ineffective region of the pixel portion, a driving method
    Type: Application
    Filed: June 17, 2016
    Publication date: December 22, 2016
    Applicant: Brillnics Japan Inc.
    Inventors: Shunsuke Okura, Shinji Ohsawa, Norio Yoshimura
  • Patent number: 8462240
    Abstract: An imaging system may include an image sensor array and column randomizing multiplexers. The imaging system may include a data output circuit and image readout circuitry such as analog amplifiers, analog-to-digital converters, and memory circuits. The column randomizing multiplexers may include a first column randomizing multiplexer between the image sensor array and at least some of the image readout circuitry. The first column randomizing multiplexer may randomly connect columns of the image sensor array to the image readout circuitry. The connections made by the first column randomizing multiplexer may be randomized as each row of the image sensor array is read out. The column randomizing multiplexers may include a second column randomizing multiplexer between at least some of the image readout circuitry and the data output circuit. The second column randomizing multiplexer may reorder image data for the image readout circuitry.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 11, 2013
    Assignee: Aptina Imaging Corporation
    Inventors: Shinji Osawa, Isao Takayanagi, Katsuyuki Kawamura, Toshiaki Sato, Norio Yoshimura, Shinichiro Matsuo, Hidenari Honda
  • Publication number: 20120062772
    Abstract: An imaging system may include an image sensor array and column randomizing multiplexers. The imaging system may include a data output circuit and image readout circuitry such as analog amplifiers, analog-to-digital converters, and memory circuits. The column randomizing multiplexers may include a first column randomizing multiplexer between the image sensor array and at least some of the image readout circuitry. The first column randomizing multiplexer may randomly connect columns of the image sensor array to the image readout circuitry. The connections made by the first column randomizing multiplexer may be randomized as each row of the image sensor array is read out. The column randomizing multiplexers may include a second column randomizing multiplexer between at least some of the image readout circuitry and the data output circuit. The second column randomizing multiplexer may reorder image data for the image readout circuitry.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 15, 2012
    Inventors: Shinji Osawa, Isao Takayanagi, Katsuyuki Kawamura, Toshiaki Sato, Norio Yoshimura, Shinichiro Matsuo, Hidenari Honda
  • Publication number: 20060202946
    Abstract: A channel data setting circuit and a light emitting element drive circuit using the channel data setting circuit are disclosed. A channel data setting circuit includes a clock unit that measures one of a low level period and a high level period of a pulse signal supplied from a single input terminal, and plural counter units in which different predetermined ranges corresponding to plural channels are set. Each of the counter units is adapted to enable a count when the period measured by the clock unit has a length within the corresponding predetermined range. The value of the count is used as a channel data item for the corresponding channel.
    Type: Application
    Filed: November 29, 2005
    Publication date: September 14, 2006
    Inventor: Norio Yoshimura