Abstract: In order to ensure isolation between a plurality of antenna elements arranged in a narrow space while reducing a size of an antenna device for a vehicle, an antenna device (100) for a vehicle includes an antenna case (101), a base (102) forming an accommodation space together with the antenna case (101), and a first antenna element (122) and a second antenna element (123) that are accommodated in the accommodation space. The first antenna element (122) and the second antenna element (123) at least transmit or receive radio waves in different frequency bands. The first antenna element (122) at least partially has a meandering shape in a first direction that intersects polarization of radio waves transmitted or received by the second antenna element (123).

Abstract: A transfer path of a multicast packet is set to an output port, from among a plurality of outputs each associated with a plurality of input ports, which is specified to output the multicast packet. The number of completed path setting processes which is the number of processes for which path setting has been completed, is counted. It is determined whether or not the number of completed processes counted is identical with the number of processes for executing the multicast communication. When it is determined that the numbers are identical with each other, it is recognized that the transfer path setting of the multicast communication has been completed.

Abstract: It is an object to speed up a vector store instruction on a memory that is divided into banks as setting a plurality of elements as a unit while minimizing an increase in physical quantity. A vector processing apparatus has a plurality of register banks and processes a data string including a plurality of data elements retained in the plurality of register banks, wherein: the plurality of register banks each have a read pointer 113 that points to a read position for reading the data elements; and the start position of the read pointer 113 is changed from one register bank to another. For example, consecutive numbers assigned to the register banks may be used as the read start positions of the respective register banks.

Abstract: An information processing device including registers (105) for holding data and an operation device (102) for executing arithmetic and logic operations on input/output data held in the register. The information processing device can issue an inter-register copy instruction for instructing data held in one register to be copied to another register. The information processing device further includes a copy information holding device (113) for reserving for execution of a data copy operation by the inter-register copy instruction from a control unit (108) so as to execute the actual copy operation simultaneously with the succeeding instruction to hide the execution time of the copy operation. Thus, in the inter-register copy instruction execution phase, a reservation for a data copy operation is stored in the copy information holding device so that the execution phase is completed without performing the actual data copy operation.

Abstract: A transfer path of a multicast packet is set to an output port, from among a plurality of outputs each associated with a plurality of input ports, which is specified to output the multicast packet. The number of completed path setting processes which is the number of processes for which path setting has been completed, is counted. It is determined whether or not the number of completed processes counted is identical with the number of processes for executing the multicast communication. When it is determined that the numbers are identical with each other, it is recognized that the transfer path setting of the multicast communication has been completed.

Abstract: It is an object to speed up a vector store instruction on a memory that is divided into banks as setting a plurality of elements as a unit while minimizing an increase in physical quantity. A vector processing apparatus has a plurality of register banks and processes a data string including a plurality of data elements retained in the plurality of register banks, wherein: the plurality of register banks each have a read pointer 113 that points to a read position for reading the data elements; and the start position of the read pointer 113 is changed from one register bank to another. For example, consecutive numbers assigned to the register banks may be used as the read start positions of the respective register banks.

Abstract: An information processing device including registers (105) for holding data and an operation device (102) for executing arithmetic and logic operations on input/output data held in the register. The information processing device can issue an inter-register copy instruction for instructing data held in one register to be copied to another register. The information processing device further includes a copy information holding device (113) for reserving for execution of a data copy operation by the inter-register copy instruction from a control unit (108) so as to execute the actual copy operation simultaneously with the succeeding instruction to hide the execution time of the copy operation. Thus, in the inter-register copy instruction execution phase, a reservation for a data copy operation is stored in the copy information holding device so that the execution phase is completed without performing the actual data copy operation.

Abstract: In a processor having a cache memory, a mechanism is provided which efficiently realizes pre-fetch/post-store for the cache memory of a large quantity of data arrayed with stride (i.e., a regular increment) on a main memory. A cache memory is provided with plural ports. A first input/output port is connected to a cache memory controller of a processor core. A second input/output port is connected to a pre-fetch/post-store circuit outside the processor core. A portion of a memory area of the cache memory is associated with a specified physical space area of a main memory device in a one-for-one correspondence and is designed as a pre-fetch/post-store cache area dedicated to the specified physical space area. For the pre-fetch/post-store cache area, the pre-fetch/post-store circuit transfers data directly with the main memory device without interfering with the cache memory controller within the processor core.