Patents by Inventor Noritaka Ide

Noritaka Ide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11951737
    Abstract: A distance between the first circuit and the second circuit is a first distance, a distance between the first circuit and the temperature detection circuit is a second distance longer than the first distance, and a distance between the second circuit and the temperature detection circuit is a third distance longer than the first distance.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 9, 2024
    Assignee: Seiko Epson Corporation
    Inventors: Shoichiro Yokoo, Noritaka Ide, Eiju Hirai, Masaki Mori, Yu Shiozawa
  • Patent number: 11919297
    Abstract: A driving circuit includes an amplification circuit that outputs an amplified modulation signal and a level shift circuit. In the level shift circuit, when a reference potential of the amplified modulation signal is shifted to a second potential from a first potential, a second gate driver outputs a third gate signal for controlling a third transistor to be nonconductive and a fourth gate signal for controlling a fourth transistor to be conductive, then outputs the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be nonconductive, and thereafter outputs the third gate signal for controlling the third transistor to be nonconductive and the fourth gate signal for controlling the fourth transistor to be conductive.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 5, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Noritaka Ide, Kunio Tabata
  • Patent number: 11919298
    Abstract: A driving circuit includes an amplification circuit configured to output an amplified modulation signal and a level shift circuit. The level shift circuit includes a second gate driver that outputs a third gate signal and a fourth gate signal, a third transistor that operates based on the third gate signal, and a fourth transistor that operates based on the fourth gate signal. The second gate driver outputs the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be nonconductive in a second period in which a driving signal is fixed in a second potential that is higher than a first potential and lower than a third potential and the fourth gate signal for controlling the fourth transistor to be nonconductive.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 5, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Noritaka Ide, Kunio Tabata
  • Publication number: 20240066859
    Abstract: A liquid ejection system includes a first head unit and a second head unit. The first head unit includes a first determining circuit that determines whether a first power supply voltage is normal, a first drive circuit that outputs a first drive signal based on the first power supply voltage, and a first ejecting head that ejects liquid The second head unit includes a second determining circuit that determines whether a second power supply voltage is normal, a second drive circuit that outputs a second drive signal based on the second power supply voltage, and a second ejecting head that ejects liquid When the first determining circuit determines that the first power supply voltage is not normal, or when the second determining circuit determines that the second power supply voltage is not normal, the first ejecting head and the second ejecting head stop ejecting the liquid.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: Kunio TABATA, Noritaka IDE, Dai NOZAWA, Rika TANIMOTO, Yukihiro HANAOKA
  • Patent number: 11904606
    Abstract: A level shift circuit and when a reference potential of the amplification modulation signal is transitioned from a first potential to a second potential having a high potential, a second gate driver performs a first control that outputs a third gate signal controlling a third transistor to be non-conductive and a fourth gate signal controlling a fourth transistor to be conductive, and then outputs the third gate signal controlling the third transistor to be conductive and the fourth gate signal controlling the fourth transistor to be non-conductive, and a second control that outputs the third gate signal controlling the third transistor to be non-conductive and the fourth gate signal controlling the fourth transistor to be conductive after the first control, and then outputs the third gate signal controlling the third transistor to be conductive and the fourth gate signal controlling the fourth transistor to be non-conductive.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 20, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Noritaka Ide, Kunio Tabata, Shoichiro Yokoo
  • Patent number: 11904607
    Abstract: An amplifier circuit, a level shift circuit; and a demodulation circuit, in which in a second mode obtained by shifting a reference potential of the amplification modulation signal to a second potential having a potential higher than a first potential, the second gate driver included in the level shift circuit performs a constant voltage control that outputs a third gate signal controlling a third transistor to be conductive and a fourth gate signal controlling a fourth transistor to be non-conductive, and a charge control that outputs the third gate signal controlling the third transistor to be non-conductive and the fourth gate signal controlling the fourth transistor to be conductive, and then outputs the third gate signal controlling the third transistor to be conductive and the fourth gate signal controlling the fourth transistor to be non-conductive.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 20, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Shoichiro Yokoo, Noritaka Ide, Kunio Tabata
  • Patent number: 11840076
    Abstract: A level shift circuit that outputs a level shift amplification modulation signal obtained by shifting a potential of an amplification modulation signal output by an amplifier circuit is provided, a potential of a first voltage supplied to one end of a first transistor of the amplifier circuit is larger than a potential of a second voltage supplied to a bootstrap circuit which is a reference of a third voltage supplied to one end of a third transistor included in the level shift circuit, and a second gate driver included in the level shift circuit outputs a third gate signal that switches an operation of the third transistor and a fourth gate signal that switches an operation of a fourth transistor, in a period during which a potential of a drive signal is between the potential of the first voltage and the potential of the second voltage.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 12, 2023
    Inventors: Noritaka Ide, Kunio Tabata
  • Patent number: 11813860
    Abstract: A first switching circuit, a second switching circuit, a first bootstrap circuit that is coupled to the first switching circuit and the second switching circuit, and a smoothing circuit and outputs a drive signal are provided, in which the second switching circuit includes a second gate driver that outputs a third gate signal and a fourth gate signal, a third transistor of which the first voltage is supplied, and which is driven based on the third gate signal, a fourth transistor which is driven based on the fourth gate signal, and a second bootstrap circuit that includes a second capacitive element supplying a third voltage to the second gate driver and coupled to a second output point and the second gate driver, and a second diode of which the first voltage is supplied and which is coupled to the second capacitive element.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: November 14, 2023
    Inventors: Kunio Tabata, Noritaka Ide, Shoichiro Yokoo
  • Publication number: 20230302787
    Abstract: A liquid discharge apparatus includes a correction circuit that outputs a correction base drive signal obtained, a level shift circuit that outputs a level shift amplified modulation signal, and a demodulation circuit that outputs the drive signal by demodulating the level shift amplified modulation signal, the correction circuit outputs the correction base drive signal corrected by a first correction value, in a first mode in which the level shift circuit outputs the level shift amplified modulation signal having the reference potential of the amplified modulation signal as a first potential, and outputs the correction base drive signal corrected by a second correction value different from the first correction value, in a second mode in which the level shift circuit outputs the level shift amplified modulation signal obtained by level-shifting the reference potential of the amplified modulation signal to a second potential different from the first potential.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 28, 2023
    Inventors: Noritaka IDE, Kunio TABATA, Shoichiro YOKOO
  • Publication number: 20230302791
    Abstract: A liquid discharge apparatus in which a level shift circuit executes, one or a plurality of times according to a voltage value of a capacitor included in a bootstrap circuit detected by a voltage detection circuit, a second control of outputting a third gate signal for controlling a third transistor to be non-conductive and a fourth gate signal for controlling a fourth transistor to be conductive, and then, outputting the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be non-conductive.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 28, 2023
    Inventors: Noritaka IDE, Kunio TABATA
  • Publication number: 20230302788
    Abstract: A liquid discharge apparatus includes a liquid discharge head that includes a plurality of capacitive loads driven by being supplied with a drive signal and discharges a liquid by driving the plurality of capacitive loads, and a capacitive load drive circuit, in which the capacitive load drive circuit includes a correction circuit, a modulation circuit, an amplification circuit, a demodulation circuit, and a feedback circuit, and the correction circuit outputs the correction base drive signal corrected according to the number of drive capacitive loads driven by the drive signal among the plurality of capacitive loads.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 28, 2023
    Inventors: Noritaka IDE, Kunio TABATA, Shoichiro YOKOO
  • Publication number: 20230294397
    Abstract: A system includes a characteristics acquirer, a selector, and a notifier. The characteristics acquirer acquires pieces of ejection characteristics information regarding ejection characteristics of a plurality of heads different from one another. The selector selects a first liquid ejecting head from among the plurality of heads based on the pieces of ejection characteristics information. The notifier notifies a user of information regarding the first liquid ejecting head.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 21, 2023
    Inventors: Noritaka IDE, Kunio TABATA, Rika TANIMOTO, Yukihiro HANAOKA, Nobuaki ITO, Naoki YAMAZAKI
  • Publication number: 20230018898
    Abstract: A liquid discharge head unit includes a liquid discharge head that has a first detection resistor that is provided to correspond to a first piezoelectric element group, a second detection resistor that is provided to correspond to a second piezoelectric element group, a power supply circuit that causes a current to flow through the first detection resistor and the second detection resistor, a voltage detection circuit that detects a voltage, and a switching circuit that is configured to switch between a first state in which the voltage detection circuit is configured to detect a voltage generated in the first detection resistor due to the current flowing from the power supply circuit and a second state in which the voltage detection circuit is configured to detect a voltage generated in the second detection resistor due to the current flowing from the power supply circuit.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 19, 2023
    Inventors: Noritaka IDE, Shoichiro YOKOO, Eiju HIRAI, Yu SHIOZAWA, Masaki MORI
  • Publication number: 20230020830
    Abstract: A distance between the first circuit and the second circuit is a first distance, a distance between the first circuit and the temperature detection circuit is a second distance longer than the first distance, and a distance between the second circuit and the temperature detection circuit is a third distance longer than the first distance.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 19, 2023
    Inventors: Shoichiro YOKOO, Noritaka IDE, Eiju HIRAI, Masaki MORI, Yu SHIOZAWA
  • Publication number: 20220169013
    Abstract: An amplifier circuit, a level shift circuit; and a demodulation circuit, in which in a second mode obtained by shifting a reference potential of the amplification modulation signal to a second potential having a potential higher than a first potential, the second gate driver included in the level shift circuit performs a constant voltage control that outputs a third gate signal controlling a third transistor to be conductive and a fourth gate signal controlling a fourth transistor to be non-conductive, and a charge control that outputs the third gate signal controlling the third transistor to be non-conductive and the fourth gate signal controlling the fourth transistor to be conductive, and then outputs the third gate signal controlling the third transistor to be conductive and the fourth gate signal controlling the fourth transistor to be non-conductive.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 2, 2022
    Inventors: Shoichiro YOKOO, Noritaka IDE, Kunio TABATA
  • Publication number: 20220169011
    Abstract: A level shift circuit that outputs a level shift amplification modulation signal obtained by shifting a potential of an amplification modulation signal output by an amplifier circuit is provided, a potential of a first voltage supplied to one end of a first transistor of the amplifier circuit is larger than a potential of a second voltage supplied to a bootstrap circuit which is a reference of a third voltage supplied to one end of a third transistor included in the level shift circuit, and a second gate driver included in the level shift circuit outputs a third gate signal that switches an operation of the third transistor and a fourth gate signal that switches an operation of a fourth transistor, in a period during which a potential of a drive signal is between the potential of the first voltage and the potential of the second voltage.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 2, 2022
    Inventors: Noritaka IDE, Kunio TABATA
  • Publication number: 20220169014
    Abstract: A first switching circuit, a second switching circuit, a first bootstrap circuit that is coupled to the first switching circuit and the second switching circuit, and a smoothing circuit and outputs a drive signal are provided, in which the second switching circuit includes a second gate driver that outputs a third gate signal and a fourth gate signal, a third transistor of which the first voltage is supplied, and which is driven based on the third gate signal, a fourth transistor which is driven based on the fourth gate signal, and a second bootstrap circuit that includes a second capacitive element supplying a third voltage to the second gate driver and coupled to a second output point and the second gate driver, and a second diode of which the first voltage is supplied and which is coupled to the second capacitive element.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 2, 2022
    Inventors: Kunio TABATA, Noritaka IDE, Shoichiro YOKOO
  • Publication number: 20220169012
    Abstract: A level shift circuit and when a reference potential of the amplification modulation signal is transitioned from a first potential to a second potential having a high potential, a second gate driver performs a first control that outputs a third gate signal controlling a third transistor to be non-conductive and a fourth gate signal controlling a fourth transistor to be conductive, and then outputs the third gate signal controlling the third transistor to be conductive and the fourth gate signal controlling the fourth transistor to be non-conductive, and a second control that outputs the third gate signal controlling the third transistor to be non-conductive and the fourth gate signal controlling the fourth transistor to be conductive after the first control, and then outputs the third gate signal controlling the third transistor to be conductive and the fourth gate signal controlling the fourth transistor to be non-conductive.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 2, 2022
    Inventors: Noritaka IDE, Kunio TABATA, Shoichiro YOKOO
  • Publication number: 20220097364
    Abstract: A driving circuit includes an amplification circuit that outputs an amplified modulation signal and a level shift circuit. In the level shift circuit, when a reference potential of the amplified modulation signal is shifted to a second potential from a first potential, a second gate driver outputs a third gate signal for controlling a third transistor to be nonconductive and a fourth gate signal for controlling a fourth transistor to be conductive, then outputs the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be nonconductive, and thereafter outputs the third gate signal for controlling the third transistor to be nonconductive and the fourth gate signal for controlling the fourth transistor to be conductive.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 31, 2022
    Inventors: Noritaka IDE, Kunio TABATA
  • Publication number: 20220097358
    Abstract: A driving circuit includes an amplification circuit configured to output an amplified modulation signal and a level shift circuit. The level shift circuit includes a second gate driver that outputs a third gate signal and a fourth gate signal, a third transistor that operates based on the third gate signal, and a fourth transistor that operates based on the fourth gate signal. The second gate driver outputs the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be nonconductive in a second period in which a driving signal is fixed in a second potential that is higher than a first potential and lower than a third potential and the fourth gate signal for controlling the fourth transistor to be nonconductive.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 31, 2022
    Inventors: Noritaka IDE, Kunio TABATA