Patents by Inventor Noritaka KAI

Noritaka KAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and memory state detecting method
    Patent number: 11183256
    Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Kioxia Corporation
    Inventors: Koichi Shinohara, Katsuki Matsudera, Ian Christopher Gamara, Yoshikazu Harada, Noritaka Kai, Yusuke Tanefusa
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY STATE DETECTING METHOD
    Publication number: 20210082531
    Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.
    Type: Application
    Filed: June 29, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Koichi SHINOHARA, Katsuki MATSUDERA, Ian Christopher GAMARA, Yoshikazu I HARADA, Noritaka KAI, Yusuke TANEFUSA