Abstract: A variable is allocated to a statement that designates an event associated with a function call in an assertion. Generation of the event at an arbitrary time on a continuous time series is detected, and a value corresponding to a meaning of the statement is assigned to the variable. Whether or not a condition corresponding to the meaning of the statement is satisfied is determined based on the value of the variable at each time on a discrete time series.

Abstract: A variable is allocated to a statement that designates an event associated with a function call in an assertion. Generation of the event at an arbitrary time on a continuous time series is detected, and a value corresponding to a meaning of the statement is assigned to the variable. Whether or not a condition corresponding to the meaning of the statement is satisfied is determined based on the value of the variable at each time on a discrete time series.

Abstract: The first model described in a software description language is converted into the second model described in a hardware description language without considering whether a plurality of parallel procedures for writing with respect to the same shared variable are contained in the first model. It is detected whether a plurality of parallel processes corresponding to the plurality of parallel procedures for writing with respect to the same shared variable exist in the second model obtained in this manner. A value solving process is generated, in which a pair of a data signal and an assignment timing signal are input from each process of all or some of the detected parallel processes, and a signal of the data signals which corresponds to a process in which the assignment timing signal has changed is output to a signal holding the value of the shared variable.

Abstract: The first model described in a software description language is converted into the second model described in a hardware description language without considering whether a plurality of parallel procedures for writing with respect to the same shared variable are contained in the first model. It is detected whether a plurality of parallel processes corresponding to the plurality of parallel procedures for writing with respect to the same shared variable exist in the second model obtained in this manner. A value solving process is generated, in which a pair of a data signal and an assignment timing signal are input from each process of all or some of the detected parallel processes, and a signal of the data signals which corresponds to a process in which the assignment timing signal has changed is output to a signal holding the value of the shared variable.

Abstract: The first model described in a software description language is converted into the second model described in a hardware description language without considering whether a plurality of parallel procedures for writing with respect to the same shared variable are contained in the first model. It is detected whether a plurality of parallel processes corresponding to the plurality of parallel procedures for writing with respect to the same shared variable exist in the second model obtained in this manner. A value solving process is generated, in which a pair of a data signal and an assignment timing signal are input from each process of all or some of the detected parallel processes, and a signal of the data signals which corresponds to a process in which the assignment timing signal has changed is output to a signal holding the value of the shared variable.